[llvm] ReduxWidth check for 0 (PR #123257)

George Chaltas via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 17 09:03:16 PST 2025


https://github.com/gchaltas updated https://github.com/llvm/llvm-project/pull/123257

>From 071217c0610373b7b21aeacfe4cb264743eca928 Mon Sep 17 00:00:00 2001
From: George Chaltas <george.chaltas at intel.com>
Date: Thu, 16 Jan 2025 12:22:59 -0800
Subject: [PATCH 1/2] ReduxWidth check for 0

Added assert to check for underflow of ReduxWidth

	modified:   llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index b0b8f8249d657b..ae08b0e5a33403 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -20080,6 +20080,7 @@ class HorizontalReduction {
         NumRegs =
             TTI.getNumberOfRegisters(TTI.getRegisterClassForType(true, Tp));
         while (NumParts > NumRegs) {
+	  assert(ReduxWidth > 0 && "ReduxWidth is unexpectedly 0.");
           ReduxWidth = bit_floor(ReduxWidth - 1);
           VectorType *Tp = getWidenedType(ScalarTy, ReduxWidth);
           NumParts = TTI.getNumberOfParts(Tp);

>From d75713c26131c07ba9e1cae4d565d8d6f3717d1e Mon Sep 17 00:00:00 2001
From: George Chaltas <george.chaltas at intel.com>
Date: Fri, 17 Jan 2025 07:59:42 -0800
Subject: [PATCH 2/2] ReduxWidtch check for 0 - formatting fixed 
 modified:   llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index ae08b0e5a33403..6e42654212967f 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -20080,7 +20080,7 @@ class HorizontalReduction {
         NumRegs =
             TTI.getNumberOfRegisters(TTI.getRegisterClassForType(true, Tp));
         while (NumParts > NumRegs) {
-	  assert(ReduxWidth > 0 && "ReduxWidth is unexpectedly 0.");
+          assert(ReduxWidth > 0 && "ReduxWidth is unexpectedly 0.");
           ReduxWidth = bit_floor(ReduxWidth - 1);
           VectorType *Tp = getWidenedType(ScalarTy, ReduxWidth);
           NumParts = TTI.getNumberOfParts(Tp);



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