[llvm] [RISCV] Select Zvkb VANDN for shorter constant loading sequences (PR #123345)

[Piotr Fusik via llvm-commits]

https://github.com/pfusik created https://github.com/llvm/llvm-project/pull/123345

This extends PR #120221 to vector instructions.

>From a8aad7b62e509b0cbd5d42553e9723f3652a7811 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Fri, 17 Jan 2025 15:09:49 +0100
Subject: [PATCH] [RISCV] Select Zvkb VANDN for shorter constant loading
 sequences

This extends PR #120221 to vector instructions.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index c69d8885175219..4aa2b881773f8e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -624,6 +624,13 @@ foreach vti = AllIntegerVectors in {
                  vti.RegClass:$rs2,
                  vti.ScalarRegClass:$rs1,
                  vti.AVL, vti.Log2SEW, TA_MA)>;
+    def : Pat<(vti.Vector (and (riscv_splat_vector invLogicImm:$rs1),
+                               vti.RegClass:$rs2)),
+              (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
+                 (vti.Vector (IMPLICIT_DEF)),
+                 vti.RegClass:$rs2,
+                 invLogicImm:$rs1,
+                 vti.AVL, vti.Log2SEW, TA_MA)>;
   }
 }