[llvm] eff6b64 - [AArch64][GlobalISel] Update and regenerate some vecreduce and other tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 17 05:19:17 PST 2025
Author: David Green
Date: 2025-01-17T13:19:11Z
New Revision: eff6b642583ace53aaed7947b92a43bcba283866
URL: https://github.com/llvm/llvm-project/commit/eff6b642583ace53aaed7947b92a43bcba283866
DIFF: https://github.com/llvm/llvm-project/commit/eff6b642583ace53aaed7947b92a43bcba283866.diff
LOG: [AArch64][GlobalISel] Update and regenerate some vecreduce and other tests. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
llvm/test/CodeGen/AArch64/aarch64-addv.ll
llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
index 253e6ebe793ce1..76fdfd0c301f6d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
@@ -6,15 +6,15 @@ tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
-
; CHECK-LABEL: name: add_v16s8
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
%2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
@@ -29,15 +29,15 @@ tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
-
; CHECK-LABEL: name: add_v8s16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
%2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
@@ -52,14 +52,14 @@ tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
-
; CHECK-LABEL: name: add_v4s32
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
- ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
%2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
@@ -73,14 +73,14 @@ tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
-
; CHECK-LABEL: name: add_v2s64
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
- ; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
+ ; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%1:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
%2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
@@ -94,14 +94,14 @@ tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
-
; CHECK-LABEL: name: add_v2s32
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
- ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
+ ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
%2:_(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
@@ -111,24 +111,25 @@ body: |
...
---
name: test_v8i64
+# This is a power-of-2 legalization, so use a tree reduction.
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $q0, $q1, $q2, $q3
- ; This is a power-of-2 legalization, so use a tree reduction.
; CHECK-LABEL: name: test_v8i64
; CHECK: liveins: $q0, $q1, $q2, $q3
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
- ; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
+ ; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
@@ -143,25 +144,26 @@ body: |
...
---
name: test_v6i64
+# This is a non-power-of-2 legalization, generate multiple vector reductions
+# and combine them with scalar ops.
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $q0, $q1, $q2, $q3
- ; This is a non-power-of-2 legalization, generate multiple vector reductions
- ; and combine them with scalar ops.
; CHECK-LABEL: name: test_v6i64
; CHECK: liveins: $q0, $q1, $q2, $q3
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY]](<2 x s64>)
- ; CHECK: [[VECREDUCE_ADD1:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY1]](<2 x s64>)
- ; CHECK: [[VECREDUCE_ADD2:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY2]](<2 x s64>)
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VECREDUCE_ADD]], [[VECREDUCE_ADD1]]
- ; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[VECREDUCE_ADD2]]
- ; CHECK: $x0 = COPY [[ADD1]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
+ ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY]](<2 x s64>)
+ ; CHECK-NEXT: [[VECREDUCE_ADD1:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY1]](<2 x s64>)
+ ; CHECK-NEXT: [[VECREDUCE_ADD2:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY2]](<2 x s64>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VECREDUCE_ADD]], [[VECREDUCE_ADD1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[VECREDUCE_ADD2]]
+ ; CHECK-NEXT: $x0 = COPY [[ADD1]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
diff --git a/llvm/test/CodeGen/AArch64/aarch64-addv.ll b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
index def4192b0e005d..aba284b4e0d292 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-addv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
@@ -1,8 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,SDAG
-; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=aarch64 -aarch64-neon-syntax=generic 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -global-isel-abort=2 -aarch64-neon-syntax=generic 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; Function Attrs: nounwind readnone
declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)
declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
@@ -23,14 +22,14 @@ declare i64 @llvm.vector.reduce.add.v3i64(<3 x i64>)
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128>)
-; GISEL: warning: Instruction selection used fallback path for addv_v2i8
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v3i8
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v4i8
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v2i16
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v3i16
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v3i32
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v3i64
-; GISEL-NEXT: warning: Instruction selection used fallback path for addv_v2i128
+; CHECK-GI: warning: Instruction selection used fallback path for addv_v2i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v4i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v2i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v2i128
define i8 @add_B(ptr %arr) {
@@ -83,34 +82,34 @@ define i64 @add_D(ptr %arr) {
define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias nocapture readonly %arg2) {
-; SDAG-LABEL: oversized_ADDV_256:
-; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: ldr d0, [x0]
-; SDAG-NEXT: ldr d1, [x1]
-; SDAG-NEXT: uabdl v0.8h, v0.8b, v1.8b
-; SDAG-NEXT: uaddlv s0, v0.8h
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: oversized_ADDV_256:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: uabdl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: uaddlv s0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: oversized_ADDV_256:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: movi v0.2d, #0000000000000000
-; GISEL-NEXT: usubl v1.8h, v1.8b, v2.8b
-; GISEL-NEXT: sshll v2.4s, v1.4h, #0
-; GISEL-NEXT: sshll2 v3.4s, v1.8h, #0
-; GISEL-NEXT: ssubw2 v0.4s, v0.4s, v1.8h
-; GISEL-NEXT: cmlt v4.4s, v2.4s, #0
-; GISEL-NEXT: cmlt v5.4s, v3.4s, #0
-; GISEL-NEXT: neg v6.4s, v2.4s
-; GISEL-NEXT: mov v1.16b, v4.16b
-; GISEL-NEXT: bif v0.16b, v3.16b, v5.16b
-; GISEL-NEXT: bsl v1.16b, v6.16b, v2.16b
-; GISEL-NEXT: add v0.4s, v1.4s, v0.4s
-; GISEL-NEXT: addv s0, v0.4s
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: oversized_ADDV_256:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: movi v0.2d, #0000000000000000
+; CHECK-GI-NEXT: usubl v1.8h, v1.8b, v2.8b
+; CHECK-GI-NEXT: sshll v2.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v1.8h, #0
+; CHECK-GI-NEXT: ssubw2 v0.4s, v0.4s, v1.8h
+; CHECK-GI-NEXT: cmlt v4.4s, v2.4s, #0
+; CHECK-GI-NEXT: cmlt v5.4s, v3.4s, #0
+; CHECK-GI-NEXT: neg v6.4s, v2.4s
+; CHECK-GI-NEXT: mov v1.16b, v4.16b
+; CHECK-GI-NEXT: bif v0.16b, v3.16b, v5.16b
+; CHECK-GI-NEXT: bsl v1.16b, v6.16b, v2.16b
+; CHECK-GI-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: fmov w0, s0
+; CHECK-GI-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %arg1, align 1
%1 = zext <8 x i8> %0 to <8 x i32>
@@ -127,48 +126,48 @@ entry:
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
define i32 @oversized_ADDV_512(ptr %arr) {
-; SDAG-LABEL: oversized_ADDV_512:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldp q0, q1, [x0, #32]
-; SDAG-NEXT: ldp q2, q3, [x0]
-; SDAG-NEXT: add v1.4s, v3.4s, v1.4s
-; SDAG-NEXT: add v0.4s, v2.4s, v0.4s
-; SDAG-NEXT: add v0.4s, v0.4s, v1.4s
-; SDAG-NEXT: addv s0, v0.4s
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: oversized_ADDV_512:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldp q0, q1, [x0, #32]
+; CHECK-SD-NEXT: ldp q2, q3, [x0]
+; CHECK-SD-NEXT: add v1.4s, v3.4s, v1.4s
+; CHECK-SD-NEXT: add v0.4s, v2.4s, v0.4s
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: addv s0, v0.4s
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: oversized_ADDV_512:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldp q0, q1, [x0]
-; GISEL-NEXT: ldp q2, q3, [x0, #32]
-; GISEL-NEXT: add v0.4s, v0.4s, v1.4s
-; GISEL-NEXT: add v1.4s, v2.4s, v3.4s
-; GISEL-NEXT: add v0.4s, v0.4s, v1.4s
-; GISEL-NEXT: addv s0, v0.4s
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: oversized_ADDV_512:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldp q0, q1, [x0]
+; CHECK-GI-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: add v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: fmov w0, s0
+; CHECK-GI-NEXT: ret
%bin.rdx = load <16 x i32>, ptr %arr
%r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %bin.rdx)
ret i32 %r
}
define i8 @addv_combine_i8(<8 x i8> %a1, <8 x i8> %a2) {
-; SDAG-LABEL: addv_combine_i8:
-; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: add v0.8b, v0.8b, v1.8b
-; SDAG-NEXT: addv b0, v0.8b
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: addv_combine_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: add v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: addv b0, v0.8b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: addv_combine_i8:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: addv b0, v0.8b
-; GISEL-NEXT: addv b1, v1.8b
-; GISEL-NEXT: fmov w8, s0
-; GISEL-NEXT: fmov w9, s1
-; GISEL-NEXT: add w0, w9, w8, uxtb
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: addv_combine_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.8b
+; CHECK-GI-NEXT: addv b1, v1.8b
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: add w0, w9, w8, uxtb
+; CHECK-GI-NEXT: ret
entry:
%rdx.1 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a1)
%rdx.2 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a2)
@@ -177,21 +176,21 @@ entry:
}
define i16 @addv_combine_i16(<4 x i16> %a1, <4 x i16> %a2) {
-; SDAG-LABEL: addv_combine_i16:
-; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: add v0.4h, v0.4h, v1.4h
-; SDAG-NEXT: addv h0, v0.4h
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: addv_combine_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: addv h0, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: addv_combine_i16:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: addv h0, v0.4h
-; GISEL-NEXT: addv h1, v1.4h
-; GISEL-NEXT: fmov w8, s0
-; GISEL-NEXT: fmov w9, s1
-; GISEL-NEXT: add w0, w9, w8, uxth
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: addv_combine_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv h0, v0.4h
+; CHECK-GI-NEXT: addv h1, v1.4h
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: add w0, w9, w8, uxth
+; CHECK-GI-NEXT: ret
entry:
%rdx.1 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a1)
%rdx.2 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a2)
@@ -200,21 +199,21 @@ entry:
}
define i32 @addv_combine_i32(<4 x i32> %a1, <4 x i32> %a2) {
-; SDAG-LABEL: addv_combine_i32:
-; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: add v0.4s, v0.4s, v1.4s
-; SDAG-NEXT: addv s0, v0.4s
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: addv_combine_i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: addv s0, v0.4s
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: addv_combine_i32:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: addv s0, v0.4s
-; GISEL-NEXT: addv s1, v1.4s
-; GISEL-NEXT: fmov w8, s0
-; GISEL-NEXT: fmov w9, s1
-; GISEL-NEXT: add w0, w8, w9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: addv_combine_i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: addv s1, v1.4s
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: add w0, w8, w9
+; CHECK-GI-NEXT: ret
entry:
%rdx.1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a1)
%rdx.2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a2)
@@ -223,21 +222,21 @@ entry:
}
define i64 @addv_combine_i64(<2 x i64> %a1, <2 x i64> %a2) {
-; SDAG-LABEL: addv_combine_i64:
-; SDAG: // %bb.0: // %entry
-; SDAG-NEXT: add v0.2d, v0.2d, v1.2d
-; SDAG-NEXT: addp d0, v0.2d
-; SDAG-NEXT: fmov x0, d0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: addv_combine_i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: addp d0, v0.2d
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: addv_combine_i64:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: addp d0, v0.2d
-; GISEL-NEXT: addp d1, v1.2d
-; GISEL-NEXT: fmov x8, d0
-; GISEL-NEXT: fmov x9, d1
-; GISEL-NEXT: add x0, x8, x9
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: addv_combine_i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addp d0, v0.2d
+; CHECK-GI-NEXT: addp d1, v1.2d
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x9, d1
+; CHECK-GI-NEXT: add x0, x8, x9
+; CHECK-GI-NEXT: ret
entry:
%rdx.1 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a1)
%rdx.2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a2)
@@ -471,3 +470,6 @@ entry:
ret i128 %arg1
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL: {{.*}}
+; SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll b/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
index b498611242d469..d69d1b6eb4a2ab 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefixes=CHECK,SDAG
-; RUN: llc < %s -global-isel -global-isel-abort=1 -pass-remarks-missed=gisel* -mtriple=arm64-linux-gnu 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL,FALLBACK
+; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
%0 = type { i64, i64 }
@@ -39,22 +39,21 @@ declare i32 @llvm.aarch64.stxp(i64, i64, ptr) nounwind
@var = dso_local global i64 0, align 8
-; FALLBACK-NOT: remark:{{.*}}test_load_i8
define dso_local void @test_load_i8(ptr %addr) {
-; SDAG-LABEL: test_load_i8:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldxrb w8, [x0]
-; SDAG-NEXT: adrp x9, var
-; SDAG-NEXT: str x8, [x9, :lo12:var]
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_load_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldxrb w8, [x0]
+; CHECK-SD-NEXT: adrp x9, var
+; CHECK-SD-NEXT: str x8, [x9, :lo12:var]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_load_i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldxrb w9, [x0]
-; GISEL-NEXT: adrp x8, var
-; GISEL-NEXT: and x9, x9, #0xff
-; GISEL-NEXT: str x9, [x8, :lo12:var]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_load_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldxrb w9, [x0]
+; CHECK-GI-NEXT: adrp x8, var
+; CHECK-GI-NEXT: and x9, x9, #0xff
+; CHECK-GI-NEXT: str x9, [x8, :lo12:var]
+; CHECK-GI-NEXT: ret
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i8) %addr)
%shortval = trunc i64 %val to i8
@@ -63,22 +62,21 @@ define dso_local void @test_load_i8(ptr %addr) {
ret void
}
-; FALLBACK-NOT: remark:{{.*}}test_load_i16
define dso_local void @test_load_i16(ptr %addr) {
-; SDAG-LABEL: test_load_i16:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldxrh w8, [x0]
-; SDAG-NEXT: adrp x9, var
-; SDAG-NEXT: str x8, [x9, :lo12:var]
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_load_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldxrh w8, [x0]
+; CHECK-SD-NEXT: adrp x9, var
+; CHECK-SD-NEXT: str x8, [x9, :lo12:var]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_load_i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldxrh w9, [x0]
-; GISEL-NEXT: adrp x8, var
-; GISEL-NEXT: and x9, x9, #0xffff
-; GISEL-NEXT: str x9, [x8, :lo12:var]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_load_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldxrh w9, [x0]
+; CHECK-GI-NEXT: adrp x8, var
+; CHECK-GI-NEXT: and x9, x9, #0xffff
+; CHECK-GI-NEXT: str x9, [x8, :lo12:var]
+; CHECK-GI-NEXT: ret
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i16) %addr)
%shortval = trunc i64 %val to i16
@@ -87,22 +85,21 @@ define dso_local void @test_load_i16(ptr %addr) {
ret void
}
-; FALLBACK-NOT: remark:{{.*}}test_load_i32
define dso_local void @test_load_i32(ptr %addr) {
-; SDAG-LABEL: test_load_i32:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldxr w8, [x0]
-; SDAG-NEXT: adrp x9, var
-; SDAG-NEXT: str x8, [x9, :lo12:var]
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_load_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldxr w8, [x0]
+; CHECK-SD-NEXT: adrp x9, var
+; CHECK-SD-NEXT: str x8, [x9, :lo12:var]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_load_i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldxr w9, [x0]
-; GISEL-NEXT: adrp x8, var
-; GISEL-NEXT: mov w9, w9
-; GISEL-NEXT: str x9, [x8, :lo12:var]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_load_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldxr w9, [x0]
+; CHECK-GI-NEXT: adrp x8, var
+; CHECK-GI-NEXT: mov w9, w9
+; CHECK-GI-NEXT: str x9, [x8, :lo12:var]
+; CHECK-GI-NEXT: ret
%val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)
%shortval = trunc i64 %val to i32
@@ -111,7 +108,6 @@ define dso_local void @test_load_i32(ptr %addr) {
ret void
}
-; FALLBACK-NOT: remark:{{.*}}test_load_i64
define dso_local void @test_load_i64(ptr %addr) {
; CHECK-LABEL: test_load_i64:
; CHECK: // %bb.0:
@@ -128,7 +124,6 @@ define dso_local void @test_load_i64(ptr %addr) {
declare i64 @llvm.aarch64.ldxr.p0(ptr) nounwind
-; FALLBACK-NOT: remark:{{.*}}test_store_i8
define dso_local i32 @test_store_i8(i32, i8 %val, ptr %addr) {
; CHECK-LABEL: test_store_i8:
; CHECK: // %bb.0:
@@ -140,7 +135,6 @@ define dso_local i32 @test_store_i8(i32, i8 %val, ptr %addr) {
ret i32 %res
}
-; FALLBACK-NOT: remark:{{.*}}test_store_i16
define dso_local i32 @test_store_i16(i32, i16 %val, ptr %addr) {
; CHECK-LABEL: test_store_i16:
; CHECK: // %bb.0:
@@ -152,7 +146,6 @@ define dso_local i32 @test_store_i16(i32, i16 %val, ptr %addr) {
ret i32 %res
}
-; FALLBACK-NOT: remark:{{.*}}test_store_i32
define dso_local i32 @test_store_i32(i32, i32 %val, ptr %addr) {
; CHECK-LABEL: test_store_i32:
; CHECK: // %bb.0:
@@ -163,7 +156,6 @@ define dso_local i32 @test_store_i32(i32, i32 %val, ptr %addr) {
ret i32 %res
}
-; FALLBACK-NOT: remark:{{.*}}test_store_i64
define dso_local i32 @test_store_i64(i32, i64 %val, ptr %addr) {
; CHECK-LABEL: test_store_i64:
; CHECK: // %bb.0:
@@ -219,22 +211,21 @@ entry:
declare %0 @llvm.aarch64.ldaxp(ptr) nounwind
declare i32 @llvm.aarch64.stlxp(i64, i64, ptr) nounwind
-; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i8
define dso_local void @test_load_acquire_i8(ptr %addr) {
-; SDAG-LABEL: test_load_acquire_i8:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldaxrb w8, [x0]
-; SDAG-NEXT: adrp x9, var
-; SDAG-NEXT: str x8, [x9, :lo12:var]
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_load_acquire_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldaxrb w8, [x0]
+; CHECK-SD-NEXT: adrp x9, var
+; CHECK-SD-NEXT: str x8, [x9, :lo12:var]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_load_acquire_i8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldaxrb w9, [x0]
-; GISEL-NEXT: adrp x8, var
-; GISEL-NEXT: and x9, x9, #0xff
-; GISEL-NEXT: str x9, [x8, :lo12:var]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_load_acquire_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldaxrb w9, [x0]
+; CHECK-GI-NEXT: adrp x8, var
+; CHECK-GI-NEXT: and x9, x9, #0xff
+; CHECK-GI-NEXT: str x9, [x8, :lo12:var]
+; CHECK-GI-NEXT: ret
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i8) %addr)
%shortval = trunc i64 %val to i8
@@ -243,22 +234,21 @@ define dso_local void @test_load_acquire_i8(ptr %addr) {
ret void
}
-; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i16
define dso_local void @test_load_acquire_i16(ptr %addr) {
-; SDAG-LABEL: test_load_acquire_i16:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldaxrh w8, [x0]
-; SDAG-NEXT: adrp x9, var
-; SDAG-NEXT: str x8, [x9, :lo12:var]
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_load_acquire_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldaxrh w8, [x0]
+; CHECK-SD-NEXT: adrp x9, var
+; CHECK-SD-NEXT: str x8, [x9, :lo12:var]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_load_acquire_i16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldaxrh w9, [x0]
-; GISEL-NEXT: adrp x8, var
-; GISEL-NEXT: and x9, x9, #0xffff
-; GISEL-NEXT: str x9, [x8, :lo12:var]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_load_acquire_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldaxrh w9, [x0]
+; CHECK-GI-NEXT: adrp x8, var
+; CHECK-GI-NEXT: and x9, x9, #0xffff
+; CHECK-GI-NEXT: str x9, [x8, :lo12:var]
+; CHECK-GI-NEXT: ret
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i16) %addr)
%shortval = trunc i64 %val to i16
@@ -267,22 +257,21 @@ define dso_local void @test_load_acquire_i16(ptr %addr) {
ret void
}
-; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i32
define dso_local void @test_load_acquire_i32(ptr %addr) {
-; SDAG-LABEL: test_load_acquire_i32:
-; SDAG: // %bb.0:
-; SDAG-NEXT: ldaxr w8, [x0]
-; SDAG-NEXT: adrp x9, var
-; SDAG-NEXT: str x8, [x9, :lo12:var]
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: test_load_acquire_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldaxr w8, [x0]
+; CHECK-SD-NEXT: adrp x9, var
+; CHECK-SD-NEXT: str x8, [x9, :lo12:var]
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: test_load_acquire_i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldaxr w9, [x0]
-; GISEL-NEXT: adrp x8, var
-; GISEL-NEXT: mov w9, w9
-; GISEL-NEXT: str x9, [x8, :lo12:var]
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: test_load_acquire_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldaxr w9, [x0]
+; CHECK-GI-NEXT: adrp x8, var
+; CHECK-GI-NEXT: mov w9, w9
+; CHECK-GI-NEXT: str x9, [x8, :lo12:var]
+; CHECK-GI-NEXT: ret
%val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i32) %addr)
%shortval = trunc i64 %val to i32
@@ -291,7 +280,6 @@ define dso_local void @test_load_acquire_i32(ptr %addr) {
ret void
}
-; FALLBACK-NOT: remark:{{.*}}test_load_acquire_i64
define dso_local void @test_load_acquire_i64(ptr %addr) {
; CHECK-LABEL: test_load_acquire_i64:
; CHECK: // %bb.0:
@@ -308,7 +296,6 @@ define dso_local void @test_load_acquire_i64(ptr %addr) {
declare i64 @llvm.aarch64.ldaxr.p0(ptr) nounwind
-; FALLBACK-NOT: remark:{{.*}}test_store_release_i8
define dso_local i32 @test_store_release_i8(i32, i8 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i8:
; CHECK: // %bb.0:
@@ -320,7 +307,6 @@ define dso_local i32 @test_store_release_i8(i32, i8 %val, ptr %addr) {
ret i32 %res
}
-; FALLBACK-NOT: remark:{{.*}}test_store_release_i16
define dso_local i32 @test_store_release_i16(i32, i16 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i16:
; CHECK: // %bb.0:
@@ -332,7 +318,6 @@ define dso_local i32 @test_store_release_i16(i32, i16 %val, ptr %addr) {
ret i32 %res
}
-; FALLBACK-NOT: remark:{{.*}}test_store_release_i32
define dso_local i32 @test_store_release_i32(i32, i32 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i32:
; CHECK: // %bb.0:
@@ -343,7 +328,6 @@ define dso_local i32 @test_store_release_i32(i32, i32 %val, ptr %addr) {
ret i32 %res
}
-; FALLBACK-NOT: remark:{{.*}}test_store_release_i64
define dso_local i32 @test_store_release_i64(i32, i64 %val, ptr %addr) {
; CHECK-LABEL: test_store_release_i64:
; CHECK: // %bb.0:
@@ -378,5 +362,3 @@ define dso_local i32 @test_stxp_undef_inline_asm(ptr %p, i64 %x) nounwind {
}
declare i32 @llvm.aarch64.stlxr.p0(i64, ptr) nounwind
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; FALLBACK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
index 7f3c1fdc93380e..c9fe258f11556d 100644
--- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
@@ -1,86 +1,87 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,SDAG
-; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -global-isel -global-isel-abort=2 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -global-isel -global-isel-abort=2 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Basic tests from input vector to bitmask
; IR generated from clang for:
; __builtin_convertvector + reinterpret_cast<uint16&>
-; GISEL: warning: Instruction selection used fallback path for clang_builtins_undef_concat_convert_to_bitmask4
-; GISEL-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_2xi32
-; GISEL-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_8xi2
-; GISEL-NEXT: warning: Instruction selection used fallback path for no_direct_convert_for_bad_concat
+; CHECK-GI: warning: Instruction selection used fallback path for convert_to_bitmask2
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for clang_builtins_undef_concat_convert_to_bitmask4
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_2xi32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_8xi2
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for no_direct_convert_for_bad_concat
define i16 @convert_to_bitmask16(<16 x i8> %vec) {
; Bits used in mask
-; SDAG-LABEL: convert_to_bitmask16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: adrp x8, lCPI0_0 at PAGE
-; SDAG-NEXT: cmeq.16b v0, v0, #0
-; SDAG-NEXT: ldr q1, [x8, lCPI0_0 at PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: ext.16b v1, v0, v0, #8
-; SDAG-NEXT: zip1.16b v0, v0, v1
-; SDAG-NEXT: addv.8h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask16:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: adrp x8, lCPI0_0 at PAGE
+; CHECK-SD-NEXT: cmeq.16b v0, v0, #0
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI0_0 at PAGEOFF]
+; CHECK-SD-NEXT: bic.16b v0, v1, v0
+; CHECK-SD-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-SD-NEXT: zip1.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.8h h0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask16:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.16b v0, v0, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: umov.b w8, v0[1]
-; GISEL-NEXT: umov.b w9, v0[0]
-; GISEL-NEXT: umov.b w10, v0[2]
-; GISEL-NEXT: umov.b w11, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w9, w8, #1, #31
-; GISEL-NEXT: and w8, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[4]
-; GISEL-NEXT: orr w8, w9, w8, lsl #2
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[5]
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[6]
-; GISEL-NEXT: orr w8, w8, w9, lsl #4
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[7]
-; GISEL-NEXT: orr w8, w8, w9, lsl #5
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[8]
-; GISEL-NEXT: orr w8, w8, w9, lsl #6
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[9]
-; GISEL-NEXT: orr w8, w8, w9, lsl #7
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[10]
-; GISEL-NEXT: orr w8, w8, w9, lsl #8
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[11]
-; GISEL-NEXT: orr w8, w8, w9, lsl #9
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[12]
-; GISEL-NEXT: orr w8, w8, w9, lsl #10
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[13]
-; GISEL-NEXT: orr w8, w8, w9, lsl #11
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[14]
-; GISEL-NEXT: orr w8, w8, w9, lsl #12
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[15]
-; GISEL-NEXT: orr w8, w8, w9, lsl #13
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #14
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #15
-; GISEL-NEXT: strh w8, [sp, #14]
-; GISEL-NEXT: and w0, w8, #0xffff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask16:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.16b v0, v0, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: umov.b w8, v0[1]
+; CHECK-GI-NEXT: umov.b w9, v0[0]
+; CHECK-GI-NEXT: umov.b w10, v0[2]
+; CHECK-GI-NEXT: umov.b w11, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w9, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[4]
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #2
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[5]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[6]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #4
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[7]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #5
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[8]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #6
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[9]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #7
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[10]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #8
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[11]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #9
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[12]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #10
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[13]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #11
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[14]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #12
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[15]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #13
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #14
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #15
+; CHECK-GI-NEXT: strh w8, [sp, #14]
+; CHECK-GI-NEXT: and w0, w8, #0xffff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
; Actual conversion
@@ -90,50 +91,50 @@ define i16 @convert_to_bitmask16(<16 x i8> %vec) {
}
define i16 @convert_to_bitmask8(<8 x i16> %vec) {
-; SDAG-LABEL: convert_to_bitmask8:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: adrp x8, lCPI1_0 at PAGE
-; SDAG-NEXT: cmeq.8h v0, v0, #0
-; SDAG-NEXT: ldr q1, [x8, lCPI1_0 at PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: addv.8h h0, v0
-; SDAG-NEXT: fmov w8, s0
-; SDAG-NEXT: and w0, w8, #0xff
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask8:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: adrp x8, lCPI1_0 at PAGE
+; CHECK-SD-NEXT: cmeq.8h v0, v0, #0
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI1_0 at PAGEOFF]
+; CHECK-SD-NEXT: bic.16b v0, v1, v0
+; CHECK-SD-NEXT: addv.8h h0, v0
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0xff
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask8:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.8h v0, v0, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: xtn.8b v0, v0
-; GISEL-NEXT: umov.b w8, v0[1]
-; GISEL-NEXT: umov.b w9, v0[0]
-; GISEL-NEXT: umov.b w10, v0[2]
-; GISEL-NEXT: umov.b w11, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w9, w8, #1, #31
-; GISEL-NEXT: and w8, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[4]
-; GISEL-NEXT: orr w8, w9, w8, lsl #2
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[5]
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[6]
-; GISEL-NEXT: orr w8, w8, w9, lsl #4
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[7]
-; GISEL-NEXT: orr w8, w8, w9, lsl #5
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #6
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #7
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask8:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.8h v0, v0, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: xtn.8b v0, v0
+; CHECK-GI-NEXT: umov.b w8, v0[1]
+; CHECK-GI-NEXT: umov.b w9, v0[0]
+; CHECK-GI-NEXT: umov.b w10, v0[2]
+; CHECK-GI-NEXT: umov.b w11, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w9, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[4]
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #2
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[5]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[6]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #4
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[7]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #5
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #6
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #7
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
@@ -143,36 +144,36 @@ define i16 @convert_to_bitmask8(<8 x i16> %vec) {
}
define i4 @convert_to_bitmask4(<4 x i32> %vec) {
-; SDAG-LABEL: convert_to_bitmask4:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: adrp x8, lCPI2_0 at PAGE
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: ldr q1, [x8, lCPI2_0 at PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask4:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: adrp x8, lCPI2_0 at PAGE
+; CHECK-SD-NEXT: cmeq.4s v0, v0, #0
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI2_0 at PAGEOFF]
+; CHECK-SD-NEXT: bic.16b v0, v1, v0
+; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask4:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask4:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.4s v0, v0, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <4 x i32> %vec, zeroinitializer
@@ -220,37 +221,37 @@ define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) {
define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_no_compare:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: adrp x8, lCPI5_0 at PAGE
-; SDAG-NEXT: ldr q1, [x8, lCPI5_0 at PAGEOFF]
-; SDAG-NEXT: shl.4s v0, v0, #31
-; SDAG-NEXT: cmlt.4s v0, v0, #0
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_no_compare:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: adrp x8, lCPI5_0 at PAGE
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI5_0 at PAGEOFF]
+; CHECK-SD-NEXT: shl.4s v0, v0, #31
+; CHECK-SD-NEXT: cmlt.4s v0, v0, #0
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_no_compare:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_no_compare:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: and.16b v0, v0, v1
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp = and <4 x i32> %vec1, %vec2
@@ -260,39 +261,39 @@ define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) {
}
define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_compare_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v2, v0, #0
-; SDAG-NEXT: cmeq.4s v0, v0, v1
-; SDAG-NEXT: adrp x8, lCPI6_0 at PAGE
-; SDAG-NEXT: ldr q1, [x8, lCPI6_0 at PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v0, v2
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_with_compare_chain:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: cmeq.4s v2, v0, #0
+; CHECK-SD-NEXT: cmeq.4s v0, v0, v1
+; CHECK-SD-NEXT: adrp x8, lCPI6_0 at PAGE
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI6_0 at PAGEOFF]
+; CHECK-SD-NEXT: bic.16b v0, v0, v2
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_with_compare_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.4s v2, v0, #0
-; GISEL-NEXT: cmeq.4s v0, v0, v1
-; GISEL-NEXT: bic.16b v0, v0, v2
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_with_compare_chain:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.4s v2, v0, #0
+; CHECK-GI-NEXT: cmeq.4s v0, v0, v1
+; CHECK-GI-NEXT: bic.16b v0, v0, v2
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
@@ -303,39 +304,39 @@ define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec
}
define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_trunc_in_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: adrp x8, lCPI7_0 at PAGE
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: ldr q1, [x8, lCPI7_0 at PAGEOFF]
-; SDAG-NEXT: shl.4s v0, v0, #31
-; SDAG-NEXT: cmlt.4s v0, v0, #0
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_with_trunc_in_chain:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: cmeq.4s v0, v0, #0
+; CHECK-SD-NEXT: adrp x8, lCPI7_0 at PAGE
+; CHECK-SD-NEXT: bic.16b v0, v1, v0
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI7_0 at PAGEOFF]
+; CHECK-SD-NEXT: shl.4s v0, v0, #31
+; CHECK-SD-NEXT: cmlt.4s v0, v0, #0
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_with_trunc_in_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: bic.16b v0, v1, v0
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_with_trunc_in_chain:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.4s v0, v0, #0
+; CHECK-GI-NEXT: bic.16b v0, v1, v0
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
@@ -346,82 +347,82 @@ define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %ve
}
define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: cmeq.4s v1, v1, #0
-; SDAG-NEXT: adrp x8, lCPI8_0 at PAGE
-; SDAG-NEXT: movi d2, #0x000000ffffffff
-; SDAG-NEXT: movi d3, #0x00ffffffffffff
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: movi d1, #0xffff0000ffff0000
-; SDAG-NEXT: xtn.4h v0, v0
-; SDAG-NEXT: orr.8b v0, v0, v2
-; SDAG-NEXT: movi d2, #0x00ffffffff0000
-; SDAG-NEXT: eor.8b v1, v0, v1
-; SDAG-NEXT: eor.8b v0, v0, v2
-; SDAG-NEXT: mov.h v1[2], wzr
-; SDAG-NEXT: orr.8b v0, v0, v3
-; SDAG-NEXT: orr.8b v0, v1, v0
-; SDAG-NEXT: ldr d1, [x8, lCPI8_0 at PAGEOFF]
-; SDAG-NEXT: shl.4h v0, v0, #15
-; SDAG-NEXT: cmlt.4h v0, v0, #0
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: cmeq.4s v0, v0, #0
+; CHECK-SD-NEXT: cmeq.4s v1, v1, #0
+; CHECK-SD-NEXT: adrp x8, lCPI8_0 at PAGE
+; CHECK-SD-NEXT: movi d2, #0x000000ffffffff
+; CHECK-SD-NEXT: movi d3, #0x00ffffffffffff
+; CHECK-SD-NEXT: bic.16b v0, v1, v0
+; CHECK-SD-NEXT: movi d1, #0xffff0000ffff0000
+; CHECK-SD-NEXT: xtn.4h v0, v0
+; CHECK-SD-NEXT: orr.8b v0, v0, v2
+; CHECK-SD-NEXT: movi d2, #0x00ffffffff0000
+; CHECK-SD-NEXT: eor.8b v1, v0, v1
+; CHECK-SD-NEXT: eor.8b v0, v0, v2
+; CHECK-SD-NEXT: mov.h v1[2], wzr
+; CHECK-SD-NEXT: orr.8b v0, v0, v3
+; CHECK-SD-NEXT: orr.8b v0, v1, v0
+; CHECK-SD-NEXT: ldr d1, [x8, lCPI8_0 at PAGEOFF]
+; CHECK-SD-NEXT: shl.4h v0, v0, #15
+; CHECK-SD-NEXT: cmlt.4h v0, v0, #0
+; CHECK-SD-NEXT: and.8b v0, v0, v1
+; CHECK-SD-NEXT: addv.4h h0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: mov w8, #1 ; =0x1
-; GISEL-NEXT: mov w9, #0 ; =0x0
-; GISEL-NEXT: cmeq.4s v5, v0, #0
-; GISEL-NEXT: fmov s2, w8
-; GISEL-NEXT: fmov s4, w9
-; GISEL-NEXT: cmeq.4s v1, v1, #0
-; GISEL-NEXT: mov.16b v3, v2
-; GISEL-NEXT: mov.16b v0, v4
-; GISEL-NEXT: mov.h v4[1], w8
-; GISEL-NEXT: bic.16b v1, v1, v5
-; GISEL-NEXT: mov.16b v5, v2
-; GISEL-NEXT: mov.h v2[1], w8
-; GISEL-NEXT: mov.h v3[1], w8
-; GISEL-NEXT: mov.h v0[1], w8
-; GISEL-NEXT: mov.h v5[1], w8
-; GISEL-NEXT: mov.h v4[2], w8
-; GISEL-NEXT: xtn.4h v1, v1
-; GISEL-NEXT: mov.h v2[2], w8
-; GISEL-NEXT: mov.h v3[2], w9
-; GISEL-NEXT: mov.h v0[2], w9
-; GISEL-NEXT: mov.h v5[2], w9
-; GISEL-NEXT: mov.h v4[3], w9
-; GISEL-NEXT: mov.h v2[3], w9
-; GISEL-NEXT: mov.h v3[3], w9
-; GISEL-NEXT: mov.h v0[3], w8
-; GISEL-NEXT: mov.h v5[3], w8
-; GISEL-NEXT: orr.8b v1, v1, v3
-; GISEL-NEXT: eor.8b v0, v1, v0
-; GISEL-NEXT: eor.8b v1, v4, v1
-; GISEL-NEXT: and.8b v0, v0, v5
-; GISEL-NEXT: orr.8b v1, v2, v1
-; GISEL-NEXT: orr.8b v0, v0, v1
-; GISEL-NEXT: ushll.4s v0, v0, #0
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w8, #1 ; =0x1
+; CHECK-GI-NEXT: mov w9, #0 ; =0x0
+; CHECK-GI-NEXT: cmeq.4s v5, v0, #0
+; CHECK-GI-NEXT: fmov s2, w8
+; CHECK-GI-NEXT: fmov s4, w9
+; CHECK-GI-NEXT: cmeq.4s v1, v1, #0
+; CHECK-GI-NEXT: mov.16b v3, v2
+; CHECK-GI-NEXT: mov.16b v0, v4
+; CHECK-GI-NEXT: mov.h v4[1], w8
+; CHECK-GI-NEXT: bic.16b v1, v1, v5
+; CHECK-GI-NEXT: mov.16b v5, v2
+; CHECK-GI-NEXT: mov.h v2[1], w8
+; CHECK-GI-NEXT: mov.h v3[1], w8
+; CHECK-GI-NEXT: mov.h v0[1], w8
+; CHECK-GI-NEXT: mov.h v5[1], w8
+; CHECK-GI-NEXT: mov.h v4[2], w8
+; CHECK-GI-NEXT: xtn.4h v1, v1
+; CHECK-GI-NEXT: mov.h v2[2], w8
+; CHECK-GI-NEXT: mov.h v3[2], w9
+; CHECK-GI-NEXT: mov.h v0[2], w9
+; CHECK-GI-NEXT: mov.h v5[2], w9
+; CHECK-GI-NEXT: mov.h v4[3], w9
+; CHECK-GI-NEXT: mov.h v2[3], w9
+; CHECK-GI-NEXT: mov.h v3[3], w9
+; CHECK-GI-NEXT: mov.h v0[3], w8
+; CHECK-GI-NEXT: mov.h v5[3], w8
+; CHECK-GI-NEXT: orr.8b v1, v1, v3
+; CHECK-GI-NEXT: eor.8b v0, v1, v0
+; CHECK-GI-NEXT: eor.8b v1, v4, v1
+; CHECK-GI-NEXT: and.8b v0, v0, v5
+; CHECK-GI-NEXT: orr.8b v1, v2, v1
+; CHECK-GI-NEXT: orr.8b v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer
@@ -440,42 +441,42 @@ define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <
}
define i4 @convert_to_bitmask_with_
diff erent_types_in_chain(<4 x i16> %vec1, <4 x i32> %vec2) {
-; SDAG-LABEL: convert_to_bitmask_with_
diff erent_types_in_chain:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmeq.4s v1, v1, #0
-; SDAG-NEXT: cmeq.4h v0, v0, #0
-; SDAG-NEXT: adrp x8, lCPI9_0 at PAGE
-; SDAG-NEXT: xtn.4h v1, v1
-; SDAG-NEXT: orn.8b v0, v1, v0
-; SDAG-NEXT: ldr d1, [x8, lCPI9_0 at PAGEOFF]
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_with_
diff erent_types_in_chain:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: cmeq.4s v1, v1, #0
+; CHECK-SD-NEXT: cmeq.4h v0, v0, #0
+; CHECK-SD-NEXT: adrp x8, lCPI9_0 at PAGE
+; CHECK-SD-NEXT: xtn.4h v1, v1
+; CHECK-SD-NEXT: orn.8b v0, v1, v0
+; CHECK-SD-NEXT: ldr d1, [x8, lCPI9_0 at PAGEOFF]
+; CHECK-SD-NEXT: and.8b v0, v0, v1
+; CHECK-SD-NEXT: addv.4h h0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_with_
diff erent_types_in_chain:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.4s v1, v1, #0
-; GISEL-NEXT: cmeq.4h v0, v0, #0
-; GISEL-NEXT: xtn.4h v1, v1
-; GISEL-NEXT: orn.8b v0, v1, v0
-; GISEL-NEXT: ushll.4s v0, v0, #0
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_with_
diff erent_types_in_chain:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.4s v1, v1, #0
+; CHECK-GI-NEXT: cmeq.4h v0, v0, #0
+; CHECK-GI-NEXT: xtn.4h v1, v1
+; CHECK-GI-NEXT: orn.8b v0, v1, v0
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp1 = icmp ne <4 x i16> %vec1, zeroinitializer
@@ -486,73 +487,73 @@ define i4 @convert_to_bitmask_with_
diff erent_types_in_chain(<4 x i16> %vec1, <4
}
define i16 @convert_to_bitmask_without_knowing_type(<16 x i1> %vec) {
-; SDAG-LABEL: convert_to_bitmask_without_knowing_type:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: shl.16b v0, v0, #7
-; SDAG-NEXT: adrp x8, lCPI10_0 at PAGE
-; SDAG-NEXT: ldr q1, [x8, lCPI10_0 at PAGEOFF]
-; SDAG-NEXT: cmlt.16b v0, v0, #0
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: ext.16b v1, v0, v0, #8
-; SDAG-NEXT: zip1.16b v0, v0, v1
-; SDAG-NEXT: addv.8h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_without_knowing_type:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: shl.16b v0, v0, #7
+; CHECK-SD-NEXT: adrp x8, lCPI10_0 at PAGE
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI10_0 at PAGEOFF]
+; CHECK-SD-NEXT: cmlt.16b v0, v0, #0
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-SD-NEXT: zip1.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.8h h0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_without_knowing_type:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: umov.b w8, v0[1]
-; GISEL-NEXT: umov.b w9, v0[0]
-; GISEL-NEXT: umov.b w10, v0[2]
-; GISEL-NEXT: umov.b w11, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w9, w8, #1, #31
-; GISEL-NEXT: and w8, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[4]
-; GISEL-NEXT: orr w8, w9, w8, lsl #2
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[5]
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[6]
-; GISEL-NEXT: orr w8, w8, w9, lsl #4
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[7]
-; GISEL-NEXT: orr w8, w8, w9, lsl #5
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[8]
-; GISEL-NEXT: orr w8, w8, w9, lsl #6
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[9]
-; GISEL-NEXT: orr w8, w8, w9, lsl #7
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[10]
-; GISEL-NEXT: orr w8, w8, w9, lsl #8
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[11]
-; GISEL-NEXT: orr w8, w8, w9, lsl #9
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[12]
-; GISEL-NEXT: orr w8, w8, w9, lsl #10
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[13]
-; GISEL-NEXT: orr w8, w8, w9, lsl #11
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[14]
-; GISEL-NEXT: orr w8, w8, w9, lsl #12
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[15]
-; GISEL-NEXT: orr w8, w8, w9, lsl #13
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #14
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #15
-; GISEL-NEXT: strh w8, [sp, #14]
-; GISEL-NEXT: and w0, w8, #0xffff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_without_knowing_type:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: umov.b w8, v0[1]
+; CHECK-GI-NEXT: umov.b w9, v0[0]
+; CHECK-GI-NEXT: umov.b w10, v0[2]
+; CHECK-GI-NEXT: umov.b w11, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w9, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[4]
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #2
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[5]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[6]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #4
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[7]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #5
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[8]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #6
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[9]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #7
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[10]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #8
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[11]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #9
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[12]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #10
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[13]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #11
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[14]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #12
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[15]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #13
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #14
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #15
+; CHECK-GI-NEXT: strh w8, [sp, #14]
+; CHECK-GI-NEXT: and w0, w8, #0xffff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%bitmask = bitcast <16 x i1> %vec to i16
ret i16 %bitmask
@@ -575,51 +576,51 @@ define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) {
}
define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) {
-; SDAG-LABEL: convert_to_bitmask_4xi8:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: bic.4h v0, #255, lsl #8
-; SDAG-NEXT: adrp x8, lCPI12_0 at PAGE
-; SDAG-NEXT: ldr d1, [x8, lCPI12_0 at PAGEOFF]
-; SDAG-NEXT: cmeq.4h v0, v0, #0
-; SDAG-NEXT: bic.8b v0, v1, v0
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_4xi8:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-SD-NEXT: adrp x8, lCPI12_0 at PAGE
+; CHECK-SD-NEXT: ldr d1, [x8, lCPI12_0 at PAGEOFF]
+; CHECK-SD-NEXT: cmeq.4h v0, v0, #0
+; CHECK-SD-NEXT: bic.8b v0, v1, v0
+; CHECK-SD-NEXT: addv.4h h0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_4xi8:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: mov w8, #0 ; =0x0
-; GISEL-NEXT: uzp1.8b v0, v0, v0
-; GISEL-NEXT: fmov s1, w8
-; GISEL-NEXT: mov.b v1[1], w8
-; GISEL-NEXT: mov.b v1[2], w8
-; GISEL-NEXT: mov.b v1[3], w8
-; GISEL-NEXT: cmeq.8b v0, v0, v1
-; GISEL-NEXT: mvn.8b v0, v0
-; GISEL-NEXT: umov.b w8, v0[0]
-; GISEL-NEXT: umov.b w9, v0[1]
-; GISEL-NEXT: mov.s v1[0], w8
-; GISEL-NEXT: umov.b w8, v0[2]
-; GISEL-NEXT: mov.s v1[1], w9
-; GISEL-NEXT: umov.b w9, v0[3]
-; GISEL-NEXT: mov.s v1[2], w8
-; GISEL-NEXT: mov.s v1[3], w9
-; GISEL-NEXT: mov.s w8, v1[1]
-; GISEL-NEXT: mov.s w9, v1[2]
-; GISEL-NEXT: fmov w11, s1
-; GISEL-NEXT: mov.s w10, v1[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_4xi8:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov w8, #0 ; =0x0
+; CHECK-GI-NEXT: uzp1.8b v0, v0, v0
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: mov.b v1[1], w8
+; CHECK-GI-NEXT: mov.b v1[2], w8
+; CHECK-GI-NEXT: mov.b v1[3], w8
+; CHECK-GI-NEXT: cmeq.8b v0, v0, v1
+; CHECK-GI-NEXT: mvn.8b v0, v0
+; CHECK-GI-NEXT: umov.b w8, v0[0]
+; CHECK-GI-NEXT: umov.b w9, v0[1]
+; CHECK-GI-NEXT: mov.s v1[0], w8
+; CHECK-GI-NEXT: umov.b w8, v0[2]
+; CHECK-GI-NEXT: mov.s v1[1], w9
+; CHECK-GI-NEXT: umov.b w9, v0[3]
+; CHECK-GI-NEXT: mov.s v1[2], w8
+; CHECK-GI-NEXT: mov.s v1[3], w9
+; CHECK-GI-NEXT: mov.s w8, v1[1]
+; CHECK-GI-NEXT: mov.s w9, v1[2]
+; CHECK-GI-NEXT: fmov w11, s1
+; CHECK-GI-NEXT: mov.s w10, v1[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <4 x i8> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4
@@ -645,39 +646,39 @@ define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
}
define i4 @convert_to_bitmask_float(<4 x float> %vec) {
-; SDAG-LABEL: convert_to_bitmask_float:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: fcmgt.4s v1, v0, #0.0
-; SDAG-NEXT: fcmlt.4s v0, v0, #0.0
-; SDAG-NEXT: adrp x8, lCPI14_0 at PAGE
-; SDAG-NEXT: orr.16b v0, v0, v1
-; SDAG-NEXT: ldr q1, [x8, lCPI14_0 at PAGEOFF]
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: addv.4s s0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_to_bitmask_float:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: fcmgt.4s v1, v0, #0.0
+; CHECK-SD-NEXT: fcmlt.4s v0, v0, #0.0
+; CHECK-SD-NEXT: adrp x8, lCPI14_0 at PAGE
+; CHECK-SD-NEXT: orr.16b v0, v0, v1
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI14_0 at PAGEOFF]
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_to_bitmask_float:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: fcmgt.4s v1, v0, #0.0
-; GISEL-NEXT: fcmlt.4s v0, v0, #0.0
-; GISEL-NEXT: orr.16b v0, v0, v1
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_to_bitmask_float:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: fcmgt.4s v1, v0, #0.0
+; CHECK-GI-NEXT: fcmlt.4s v0, v0, #0.0
+; CHECK-GI-NEXT: orr.16b v0, v0, v1
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = fcmp one <4 x float> %vec, zeroinitializer
@@ -688,58 +689,58 @@ define i4 @convert_to_bitmask_float(<4 x float> %vec) {
; Larger vector types don't map directly, but the can be split/truncated and then converted.
; After the comparison against 0, this is truncated to <8 x i16>, which is valid again.
define i8 @convert_large_vector(<8 x i32> %vec) {
-; SDAG-LABEL: convert_large_vector:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: sub sp, sp, #16
-; SDAG-NEXT: .cfi_def_cfa_offset 16
-; SDAG-NEXT: cmeq.4s v1, v1, #0
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: adrp x8, lCPI15_0 at PAGE
-; SDAG-NEXT: uzp1.8h v0, v0, v1
-; SDAG-NEXT: ldr q1, [x8, lCPI15_0 at PAGEOFF]
-; SDAG-NEXT: bic.16b v0, v1, v0
-; SDAG-NEXT: addv.8h h0, v0
-; SDAG-NEXT: fmov w8, s0
-; SDAG-NEXT: and w0, w8, #0xff
-; SDAG-NEXT: add sp, sp, #16
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_large_vector:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: cmeq.4s v1, v1, #0
+; CHECK-SD-NEXT: cmeq.4s v0, v0, #0
+; CHECK-SD-NEXT: adrp x8, lCPI15_0 at PAGE
+; CHECK-SD-NEXT: uzp1.8h v0, v0, v1
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI15_0 at PAGEOFF]
+; CHECK-SD-NEXT: bic.16b v0, v1, v0
+; CHECK-SD-NEXT: addv.8h h0, v0
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0xff
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_large_vector:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: cmeq.4s v1, v1, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: mvn.16b v1, v1
-; GISEL-NEXT: uzp1.8h v0, v0, v1
-; GISEL-NEXT: xtn.8b v0, v0
-; GISEL-NEXT: umov.b w8, v0[1]
-; GISEL-NEXT: umov.b w9, v0[0]
-; GISEL-NEXT: umov.b w10, v0[2]
-; GISEL-NEXT: umov.b w11, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w9, w8, #1, #31
-; GISEL-NEXT: and w8, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[4]
-; GISEL-NEXT: orr w8, w9, w8, lsl #2
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[5]
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: umov.b w10, v0[6]
-; GISEL-NEXT: orr w8, w8, w9, lsl #4
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.b w11, v0[7]
-; GISEL-NEXT: orr w8, w8, w9, lsl #5
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #6
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #7
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_large_vector:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: cmeq.4s v0, v0, #0
+; CHECK-GI-NEXT: cmeq.4s v1, v1, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: mvn.16b v1, v1
+; CHECK-GI-NEXT: uzp1.8h v0, v0, v1
+; CHECK-GI-NEXT: xtn.8b v0, v0
+; CHECK-GI-NEXT: umov.b w8, v0[1]
+; CHECK-GI-NEXT: umov.b w9, v0[0]
+; CHECK-GI-NEXT: umov.b w10, v0[2]
+; CHECK-GI-NEXT: umov.b w11, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w9, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[4]
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #2
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[5]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: umov.b w10, v0[6]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #4
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[7]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #5
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #6
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #7
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <8 x i32> %vec, zeroinitializer
@@ -748,40 +749,40 @@ define i8 @convert_large_vector(<8 x i32> %vec) {
}
define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) {
-; SDAG-LABEL: convert_legalized_illegal_element_size:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: movi.4s v1, #63, msl #16
-; SDAG-NEXT: adrp x8, lCPI16_0 at PAGE
-; SDAG-NEXT: cmtst.4s v0, v0, v1
-; SDAG-NEXT: ldr d1, [x8, lCPI16_0 at PAGEOFF]
-; SDAG-NEXT: xtn.4h v0, v0
-; SDAG-NEXT: and.8b v0, v0, v1
-; SDAG-NEXT: addv.4h h0, v0
-; SDAG-NEXT: fmov w0, s0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: convert_legalized_illegal_element_size:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: movi.4s v1, #63, msl #16
+; CHECK-SD-NEXT: adrp x8, lCPI16_0 at PAGE
+; CHECK-SD-NEXT: cmtst.4s v0, v0, v1
+; CHECK-SD-NEXT: ldr d1, [x8, lCPI16_0 at PAGEOFF]
+; CHECK-SD-NEXT: xtn.4h v0, v0
+; CHECK-SD-NEXT: and.8b v0, v0, v1
+; CHECK-SD-NEXT: addv.4h h0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: convert_legalized_illegal_element_size:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: movi.4s v1, #63, msl #16
-; GISEL-NEXT: and.16b v0, v0, v1
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: fmov w11, s0
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w11, w8, #1, #31
-; GISEL-NEXT: and w8, w9, #0x1
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w11, w8, lsl #2
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: convert_legalized_illegal_element_size:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: movi.4s v1, #63, msl #16
+; CHECK-GI-NEXT: and.16b v0, v0, v1
+; CHECK-GI-NEXT: cmeq.4s v0, v0, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: fmov w11, s0
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w11, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w9, #0x1
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <4 x i22> %vec, zeroinitializer
%bitmask = bitcast <4 x i1> %cmp_result to i4
@@ -818,101 +819,101 @@ define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) {
}
define <8 x i1> @no_convert_without_direct_bitcast(<8 x i16> %vec) {
-; SDAG-LABEL: no_convert_without_direct_bitcast:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: cmtst.8h v0, v0, v0
-; SDAG-NEXT: xtn.8b v0, v0
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: no_convert_without_direct_bitcast:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: cmtst.8h v0, v0, v0
+; CHECK-SD-NEXT: xtn.8b v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: no_convert_without_direct_bitcast:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: cmeq.8h v0, v0, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: xtn.8b v0, v0
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: no_convert_without_direct_bitcast:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: cmeq.8h v0, v0, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: xtn.8b v0, v0
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <8 x i16> %vec, zeroinitializer
ret <8 x i1> %cmp_result
}
define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) {
-; SDAG-LABEL: no_combine_illegal_num_elements:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: sub sp, sp, #16
-; SDAG-NEXT: .cfi_def_cfa_offset 16
-; SDAG-NEXT: fmov s0, w0
-; SDAG-NEXT: fmov s1, w4
-; SDAG-NEXT: mov.s v0[1], w1
-; SDAG-NEXT: mov.s v1[1], w5
-; SDAG-NEXT: mov.s v0[2], w2
-; SDAG-NEXT: cmeq.4s v1, v1, #0
-; SDAG-NEXT: mov.s v0[3], w3
-; SDAG-NEXT: cmeq.4s v0, v0, #0
-; SDAG-NEXT: uzp1.8h v0, v0, v1
-; SDAG-NEXT: mvn.16b v0, v0
-; SDAG-NEXT: xtn.8b v0, v0
-; SDAG-NEXT: umov.b w8, v0[0]
-; SDAG-NEXT: umov.b w9, v0[1]
-; SDAG-NEXT: umov.b w10, v0[2]
-; SDAG-NEXT: and w8, w8, #0x1
-; SDAG-NEXT: bfi w8, w9, #1, #1
-; SDAG-NEXT: umov.b w9, v0[3]
-; SDAG-NEXT: bfi w8, w10, #2, #1
-; SDAG-NEXT: umov.b w10, v0[4]
-; SDAG-NEXT: bfi w8, w9, #3, #1
-; SDAG-NEXT: umov.b w9, v0[5]
-; SDAG-NEXT: bfi w8, w10, #4, #1
-; SDAG-NEXT: orr w8, w8, w9, lsl #5
-; SDAG-NEXT: and w0, w8, #0x3f
-; SDAG-NEXT: add sp, sp, #16
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: no_combine_illegal_num_elements:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
+; CHECK-SD-NEXT: fmov s0, w0
+; CHECK-SD-NEXT: fmov s1, w4
+; CHECK-SD-NEXT: mov.s v0[1], w1
+; CHECK-SD-NEXT: mov.s v1[1], w5
+; CHECK-SD-NEXT: mov.s v0[2], w2
+; CHECK-SD-NEXT: cmeq.4s v1, v1, #0
+; CHECK-SD-NEXT: mov.s v0[3], w3
+; CHECK-SD-NEXT: cmeq.4s v0, v0, #0
+; CHECK-SD-NEXT: uzp1.8h v0, v0, v1
+; CHECK-SD-NEXT: mvn.16b v0, v0
+; CHECK-SD-NEXT: xtn.8b v0, v0
+; CHECK-SD-NEXT: umov.b w8, v0[0]
+; CHECK-SD-NEXT: umov.b w9, v0[1]
+; CHECK-SD-NEXT: umov.b w10, v0[2]
+; CHECK-SD-NEXT: and w8, w8, #0x1
+; CHECK-SD-NEXT: bfi w8, w9, #1, #1
+; CHECK-SD-NEXT: umov.b w9, v0[3]
+; CHECK-SD-NEXT: bfi w8, w10, #2, #1
+; CHECK-SD-NEXT: umov.b w10, v0[4]
+; CHECK-SD-NEXT: bfi w8, w9, #3, #1
+; CHECK-SD-NEXT: umov.b w9, v0[5]
+; CHECK-SD-NEXT: bfi w8, w10, #4, #1
+; CHECK-SD-NEXT: orr w8, w8, w9, lsl #5
+; CHECK-SD-NEXT: and w0, w8, #0x3f
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: no_combine_illegal_num_elements:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: .cfi_def_cfa_offset 16
-; GISEL-NEXT: mov.s v0[0], w0
-; GISEL-NEXT: mov.s v1[0], w4
-; GISEL-NEXT: mov.s v2[0], wzr
-; GISEL-NEXT: mov.s v0[1], w1
-; GISEL-NEXT: mov.s v1[1], w5
-; GISEL-NEXT: mov.s v2[1], wzr
-; GISEL-NEXT: mov.s v0[2], w2
-; GISEL-NEXT: cmeq.4s v1, v1, v2
-; GISEL-NEXT: mvn.16b v1, v1
-; GISEL-NEXT: mov.s v0[3], w3
-; GISEL-NEXT: cmeq.4s v0, v0, #0
-; GISEL-NEXT: mvn.16b v0, v0
-; GISEL-NEXT: mov.s w8, v0[1]
-; GISEL-NEXT: mov.s w9, v0[2]
-; GISEL-NEXT: mov.s w10, v0[3]
-; GISEL-NEXT: mov.h v0[1], w8
-; GISEL-NEXT: mov.s w8, v1[1]
-; GISEL-NEXT: mov.h v0[2], w9
-; GISEL-NEXT: mov.h v0[3], w10
-; GISEL-NEXT: mov.h v0[4], v1[0]
-; GISEL-NEXT: mov.h v0[5], w8
-; GISEL-NEXT: umov.h w8, v0[1]
-; GISEL-NEXT: umov.h w9, v0[0]
-; GISEL-NEXT: umov.h w10, v0[2]
-; GISEL-NEXT: umov.h w11, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: bfi w9, w8, #1, #31
-; GISEL-NEXT: and w8, w10, #0x1
-; GISEL-NEXT: umov.h w10, v0[4]
-; GISEL-NEXT: orr w8, w9, w8, lsl #2
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: umov.h w11, v0[5]
-; GISEL-NEXT: orr w8, w8, w9, lsl #3
-; GISEL-NEXT: and w9, w10, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #4
-; GISEL-NEXT: and w9, w11, #0x1
-; GISEL-NEXT: orr w8, w8, w9, lsl #5
-; GISEL-NEXT: and w8, w8, #0x3f
-; GISEL-NEXT: strb w8, [sp, #15]
-; GISEL-NEXT: and w0, w8, #0xff
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: no_combine_illegal_num_elements:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
+; CHECK-GI-NEXT: mov.s v0[0], w0
+; CHECK-GI-NEXT: mov.s v1[0], w4
+; CHECK-GI-NEXT: mov.s v2[0], wzr
+; CHECK-GI-NEXT: mov.s v0[1], w1
+; CHECK-GI-NEXT: mov.s v1[1], w5
+; CHECK-GI-NEXT: mov.s v2[1], wzr
+; CHECK-GI-NEXT: mov.s v0[2], w2
+; CHECK-GI-NEXT: cmeq.4s v1, v1, v2
+; CHECK-GI-NEXT: mvn.16b v1, v1
+; CHECK-GI-NEXT: mov.s v0[3], w3
+; CHECK-GI-NEXT: cmeq.4s v0, v0, #0
+; CHECK-GI-NEXT: mvn.16b v0, v0
+; CHECK-GI-NEXT: mov.s w8, v0[1]
+; CHECK-GI-NEXT: mov.s w9, v0[2]
+; CHECK-GI-NEXT: mov.s w10, v0[3]
+; CHECK-GI-NEXT: mov.h v0[1], w8
+; CHECK-GI-NEXT: mov.s w8, v1[1]
+; CHECK-GI-NEXT: mov.h v0[2], w9
+; CHECK-GI-NEXT: mov.h v0[3], w10
+; CHECK-GI-NEXT: mov.h v0[4], v1[0]
+; CHECK-GI-NEXT: mov.h v0[5], w8
+; CHECK-GI-NEXT: umov.h w8, v0[1]
+; CHECK-GI-NEXT: umov.h w9, v0[0]
+; CHECK-GI-NEXT: umov.h w10, v0[2]
+; CHECK-GI-NEXT: umov.h w11, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: bfi w9, w8, #1, #31
+; CHECK-GI-NEXT: and w8, w10, #0x1
+; CHECK-GI-NEXT: umov.h w10, v0[4]
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #2
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: umov.h w11, v0[5]
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
+; CHECK-GI-NEXT: and w9, w10, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #4
+; CHECK-GI-NEXT: and w9, w11, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w9, lsl #5
+; CHECK-GI-NEXT: and w8, w8, #0x3f
+; CHECK-GI-NEXT: strb w8, [sp, #15]
+; CHECK-GI-NEXT: and w0, w8, #0xff
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%cmp_result = icmp ne <6 x i32> %vec, zeroinitializer
%bitmask = bitcast <6 x i1> %cmp_result to i6
@@ -921,220 +922,220 @@ define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) {
; Only apply the combine when casting a vector to a scalar.
define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg) nounwind {
-; SDAG-LABEL: vector_to_vector_cast:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: sub sp, sp, #16
-; SDAG-NEXT: shl.16b v0, v0, #7
-; SDAG-NEXT: adrp x8, lCPI20_0 at PAGE
-; SDAG-NEXT: ldr q1, [x8, lCPI20_0 at PAGEOFF]
-; SDAG-NEXT: add x8, sp, #14
-; SDAG-NEXT: cmlt.16b v0, v0, #0
-; SDAG-NEXT: and.16b v0, v0, v1
-; SDAG-NEXT: ext.16b v1, v0, v0, #8
-; SDAG-NEXT: zip1.16b v0, v0, v1
-; SDAG-NEXT: addv.8h h0, v0
-; SDAG-NEXT: str h0, [sp, #14]
-; SDAG-NEXT: ld1.b { v0 }[0], [x8]
-; SDAG-NEXT: orr x8, x8, #0x1
-; SDAG-NEXT: ld1.b { v0 }[4], [x8]
-; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0
-; SDAG-NEXT: add sp, sp, #16
-; SDAG-NEXT: ret
+; CHECK-SD-LABEL: vector_to_vector_cast:
+; CHECK-SD: ; %bb.0:
+; CHECK-SD-NEXT: sub sp, sp, #16
+; CHECK-SD-NEXT: shl.16b v0, v0, #7
+; CHECK-SD-NEXT: adrp x8, lCPI20_0 at PAGE
+; CHECK-SD-NEXT: ldr q1, [x8, lCPI20_0 at PAGEOFF]
+; CHECK-SD-NEXT: add x8, sp, #14
+; CHECK-SD-NEXT: cmlt.16b v0, v0, #0
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-SD-NEXT: zip1.16b v0, v0, v1
+; CHECK-SD-NEXT: addv.8h h0, v0
+; CHECK-SD-NEXT: str h0, [sp, #14]
+; CHECK-SD-NEXT: ld1.b { v0 }[0], [x8]
+; CHECK-SD-NEXT: orr x8, x8, #0x1
+; CHECK-SD-NEXT: ld1.b { v0 }[4], [x8]
+; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: add sp, sp, #16
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: vector_to_vector_cast:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: sub sp, sp, #16
-; GISEL-NEXT: umov.b w8, v0[1]
-; GISEL-NEXT: mov d1, v0[1]
-; GISEL-NEXT: umov.b w10, v0[1]
-; GISEL-NEXT: umov.b w9, v0[0]
-; GISEL-NEXT: umov.b w13, v0[0]
-; GISEL-NEXT: umov.b w14, v0[2]
-; GISEL-NEXT: umov.b w15, v0[3]
-; GISEL-NEXT: umov.b w11, v0[2]
-; GISEL-NEXT: umov.b w16, v0[4]
-; GISEL-NEXT: umov.b w17, v0[5]
-; GISEL-NEXT: umov.b w12, v0[3]
-; GISEL-NEXT: and w8, w8, #0x1
-; GISEL-NEXT: and w10, w10, #0x1
-; GISEL-NEXT: umov.b w0, v1[1]
-; GISEL-NEXT: bfi w9, w8, #1, #31
-; GISEL-NEXT: bfi w13, w10, #1, #31
-; GISEL-NEXT: and w14, w14, #0x1
-; GISEL-NEXT: umov.b w8, v1[0]
-; GISEL-NEXT: umov.b w10, v1[2]
-; GISEL-NEXT: and w15, w15, #0x1
-; GISEL-NEXT: orr w13, w13, w14, lsl #2
-; GISEL-NEXT: umov.b w14, v1[3]
-; GISEL-NEXT: and w11, w11, #0x1
-; GISEL-NEXT: and w0, w0, #0x1
-; GISEL-NEXT: and w16, w16, #0x1
-; GISEL-NEXT: orr w9, w9, w11, lsl #2
-; GISEL-NEXT: orr w13, w13, w15, lsl #3
-; GISEL-NEXT: umov.b w15, v1[4]
-; GISEL-NEXT: umov.b w11, v0[6]
-; GISEL-NEXT: bfi w8, w0, #1, #31
-; GISEL-NEXT: and w10, w10, #0x1
-; GISEL-NEXT: and w17, w17, #0x1
-; GISEL-NEXT: orr w13, w13, w16, lsl #4
-; GISEL-NEXT: and w14, w14, #0x1
-; GISEL-NEXT: umov.b w0, v0[7]
-; GISEL-NEXT: orr w8, w8, w10, lsl #2
-; GISEL-NEXT: umov.b w10, v1[5]
-; GISEL-NEXT: umov.b w16, v1[6]
-; GISEL-NEXT: orr w13, w13, w17, lsl #5
-; GISEL-NEXT: umov.b w17, v0[4]
-; GISEL-NEXT: and w15, w15, #0x1
-; GISEL-NEXT: orr w8, w8, w14, lsl #3
-; GISEL-NEXT: and w12, w12, #0x1
-; GISEL-NEXT: and w11, w11, #0x1
-; GISEL-NEXT: umov.b w14, v1[7]
-; GISEL-NEXT: orr w9, w9, w12, lsl #3
-; GISEL-NEXT: orr w11, w13, w11, lsl #6
-; GISEL-NEXT: orr w8, w8, w15, lsl #4
-; GISEL-NEXT: umov.b w15, v0[5]
-; GISEL-NEXT: and w10, w10, #0x1
-; GISEL-NEXT: and w0, w0, #0x1
-; GISEL-NEXT: and w12, w17, #0x1
-; GISEL-NEXT: umov.b w13, v0[1]
-; GISEL-NEXT: orr w8, w8, w10, lsl #5
-; GISEL-NEXT: and w16, w16, #0x1
-; GISEL-NEXT: orr w9, w9, w12, lsl #4
-; GISEL-NEXT: umov.b w10, v0[0]
-; GISEL-NEXT: orr w11, w11, w0, lsl #7
-; GISEL-NEXT: and w14, w14, #0x1
-; GISEL-NEXT: and w12, w15, #0x1
-; GISEL-NEXT: umov.b w15, v0[2]
-; GISEL-NEXT: orr w8, w8, w16, lsl #6
-; GISEL-NEXT: orr w9, w9, w12, lsl #5
-; GISEL-NEXT: umov.b w12, v0[6]
-; GISEL-NEXT: strb w11, [sp, #8]
-; GISEL-NEXT: and w11, w13, #0x1
-; GISEL-NEXT: umov.b w13, v0[3]
-; GISEL-NEXT: orr w8, w8, w14, lsl #7
-; GISEL-NEXT: umov.b w14, v0[7]
-; GISEL-NEXT: ldr b0, [sp, #8]
-; GISEL-NEXT: bfi w10, w11, #1, #31
-; GISEL-NEXT: and w11, w15, #0x1
-; GISEL-NEXT: strb w8, [sp, #9]
-; GISEL-NEXT: umov.b w15, v0[4]
-; GISEL-NEXT: and w8, w12, #0x1
-; GISEL-NEXT: orr w10, w10, w11, lsl #2
-; GISEL-NEXT: orr w8, w9, w8, lsl #6
-; GISEL-NEXT: and w9, w13, #0x1
-; GISEL-NEXT: umov.b w11, v0[1]
-; GISEL-NEXT: orr w9, w10, w9, lsl #3
-; GISEL-NEXT: umov.b w10, v0[5]
-; GISEL-NEXT: umov.b w12, v0[0]
-; GISEL-NEXT: and w13, w14, #0x1
-; GISEL-NEXT: umov.b w16, v0[2]
-; GISEL-NEXT: umov.b w17, v0[3]
-; GISEL-NEXT: and w14, w15, #0x1
-; GISEL-NEXT: umov.b w15, v0[2]
-; GISEL-NEXT: orr w8, w8, w13, lsl #7
-; GISEL-NEXT: orr w9, w9, w14, lsl #4
-; GISEL-NEXT: umov.b w13, v0[6]
-; GISEL-NEXT: and w11, w11, #0x1
-; GISEL-NEXT: umov.b w14, v0[3]
-; GISEL-NEXT: strb w8, [sp, #10]
-; GISEL-NEXT: and w8, w10, #0x1
-; GISEL-NEXT: bfi w12, w11, #1, #31
-; GISEL-NEXT: orr w8, w9, w8, lsl #5
-; GISEL-NEXT: umov.b w10, v0[4]
-; GISEL-NEXT: and w9, w15, #0x1
-; GISEL-NEXT: umov.b w11, v0[7]
-; GISEL-NEXT: umov.b w15, v0[1]
-; GISEL-NEXT: orr w9, w12, w9, lsl #2
-; GISEL-NEXT: umov.b w12, v0[5]
-; GISEL-NEXT: and w13, w13, #0x1
-; GISEL-NEXT: and w14, w14, #0x1
-; GISEL-NEXT: orr w8, w8, w13, lsl #6
-; GISEL-NEXT: umov.b w13, v0[0]
-; GISEL-NEXT: orr w9, w9, w14, lsl #3
-; GISEL-NEXT: and w10, w10, #0x1
-; GISEL-NEXT: umov.b w14, v0[6]
-; GISEL-NEXT: and w11, w11, #0x1
-; GISEL-NEXT: and w15, w15, #0x1
-; GISEL-NEXT: umov.b w0, v0[3]
-; GISEL-NEXT: orr w9, w9, w10, lsl #4
-; GISEL-NEXT: and w10, w12, #0x1
-; GISEL-NEXT: umov.b w12, v0[7]
-; GISEL-NEXT: orr w8, w8, w11, lsl #7
-; GISEL-NEXT: bfi w13, w15, #1, #31
-; GISEL-NEXT: and w11, w16, #0x1
-; GISEL-NEXT: orr w9, w9, w10, lsl #5
-; GISEL-NEXT: and w10, w14, #0x1
-; GISEL-NEXT: umov.b w14, v0[4]
-; GISEL-NEXT: strb w8, [sp, #11]
-; GISEL-NEXT: umov.b w15, v0[1]
-; GISEL-NEXT: umov.b w16, v0[3]
-; GISEL-NEXT: orr w8, w9, w10, lsl #6
-; GISEL-NEXT: orr w9, w13, w11, lsl #2
-; GISEL-NEXT: and w10, w12, #0x1
-; GISEL-NEXT: and w11, w17, #0x1
-; GISEL-NEXT: umov.b w12, v0[5]
-; GISEL-NEXT: umov.b w17, v0[0]
-; GISEL-NEXT: orr w8, w8, w10, lsl #7
-; GISEL-NEXT: orr w9, w9, w11, lsl #3
-; GISEL-NEXT: umov.b w10, v0[1]
-; GISEL-NEXT: and w11, w14, #0x1
-; GISEL-NEXT: umov.b w14, v0[0]
-; GISEL-NEXT: and w15, w15, #0x1
-; GISEL-NEXT: orr w9, w9, w11, lsl #4
-; GISEL-NEXT: umov.b w11, v0[2]
-; GISEL-NEXT: umov.b w13, v0[6]
-; GISEL-NEXT: and w12, w12, #0x1
-; GISEL-NEXT: bfi w17, w15, #1, #31
-; GISEL-NEXT: umov.b w15, v0[5]
-; GISEL-NEXT: orr w9, w9, w12, lsl #5
-; GISEL-NEXT: and w10, w10, #0x1
-; GISEL-NEXT: umov.b w12, v0[2]
-; GISEL-NEXT: bfi w14, w10, #1, #31
-; GISEL-NEXT: umov.b w10, v0[4]
-; GISEL-NEXT: ldr b1, [sp, #9]
-; GISEL-NEXT: and w11, w11, #0x1
-; GISEL-NEXT: and w13, w13, #0x1
-; GISEL-NEXT: strb w8, [sp, #12]
-; GISEL-NEXT: orr w11, w14, w11, lsl #2
-; GISEL-NEXT: and w14, w16, #0x1
-; GISEL-NEXT: umov.b w16, v0[4]
-; GISEL-NEXT: and w12, w12, #0x1
-; GISEL-NEXT: and w15, w15, #0x1
-; GISEL-NEXT: orr w9, w9, w13, lsl #6
-; GISEL-NEXT: orr w11, w11, w14, lsl #3
-; GISEL-NEXT: orr w12, w17, w12, lsl #2
-; GISEL-NEXT: and w10, w10, #0x1
-; GISEL-NEXT: and w17, w0, #0x1
-; GISEL-NEXT: umov.b w0, v0[5]
-; GISEL-NEXT: umov.b w14, v0[6]
-; GISEL-NEXT: orr w10, w11, w10, lsl #4
-; GISEL-NEXT: orr w12, w12, w17, lsl #3
-; GISEL-NEXT: umov.b w11, v0[7]
-; GISEL-NEXT: and w16, w16, #0x1
-; GISEL-NEXT: umov.b w17, v0[6]
-; GISEL-NEXT: orr w10, w10, w15, lsl #5
-; GISEL-NEXT: umov.b w15, v0[7]
-; GISEL-NEXT: orr w12, w12, w16, lsl #4
-; GISEL-NEXT: and w16, w0, #0x1
-; GISEL-NEXT: umov.b w0, v0[7]
-; GISEL-NEXT: and w14, w14, #0x1
-; GISEL-NEXT: orr w12, w12, w16, lsl #5
-; GISEL-NEXT: orr w10, w10, w14, lsl #6
-; GISEL-NEXT: and w11, w11, #0x1
-; GISEL-NEXT: and w13, w17, #0x1
-; GISEL-NEXT: orr w9, w9, w11, lsl #7
-; GISEL-NEXT: mov.s v0[1], v1[0]
-; GISEL-NEXT: orr w11, w12, w13, lsl #6
-; GISEL-NEXT: and w12, w15, #0x1
-; GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0
-; GISEL-NEXT: orr w8, w10, w12, lsl #7
-; GISEL-NEXT: and w10, w0, #0x1
-; GISEL-NEXT: strb w9, [sp, #13]
-; GISEL-NEXT: orr w9, w11, w10, lsl #7
-; GISEL-NEXT: strb w8, [sp, #14]
-; GISEL-NEXT: strb w9, [sp, #15]
-; GISEL-NEXT: add sp, sp, #16
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: vector_to_vector_cast:
+; CHECK-GI: ; %bb.0:
+; CHECK-GI-NEXT: sub sp, sp, #16
+; CHECK-GI-NEXT: umov.b w8, v0[1]
+; CHECK-GI-NEXT: mov d1, v0[1]
+; CHECK-GI-NEXT: umov.b w10, v0[1]
+; CHECK-GI-NEXT: umov.b w9, v0[0]
+; CHECK-GI-NEXT: umov.b w13, v0[0]
+; CHECK-GI-NEXT: umov.b w14, v0[2]
+; CHECK-GI-NEXT: umov.b w15, v0[3]
+; CHECK-GI-NEXT: umov.b w11, v0[2]
+; CHECK-GI-NEXT: umov.b w16, v0[4]
+; CHECK-GI-NEXT: umov.b w17, v0[5]
+; CHECK-GI-NEXT: umov.b w12, v0[3]
+; CHECK-GI-NEXT: and w8, w8, #0x1
+; CHECK-GI-NEXT: and w10, w10, #0x1
+; CHECK-GI-NEXT: umov.b w0, v1[1]
+; CHECK-GI-NEXT: bfi w9, w8, #1, #31
+; CHECK-GI-NEXT: bfi w13, w10, #1, #31
+; CHECK-GI-NEXT: and w14, w14, #0x1
+; CHECK-GI-NEXT: umov.b w8, v1[0]
+; CHECK-GI-NEXT: umov.b w10, v1[2]
+; CHECK-GI-NEXT: and w15, w15, #0x1
+; CHECK-GI-NEXT: orr w13, w13, w14, lsl #2
+; CHECK-GI-NEXT: umov.b w14, v1[3]
+; CHECK-GI-NEXT: and w11, w11, #0x1
+; CHECK-GI-NEXT: and w0, w0, #0x1
+; CHECK-GI-NEXT: and w16, w16, #0x1
+; CHECK-GI-NEXT: orr w9, w9, w11, lsl #2
+; CHECK-GI-NEXT: orr w13, w13, w15, lsl #3
+; CHECK-GI-NEXT: umov.b w15, v1[4]
+; CHECK-GI-NEXT: umov.b w11, v0[6]
+; CHECK-GI-NEXT: bfi w8, w0, #1, #31
+; CHECK-GI-NEXT: and w10, w10, #0x1
+; CHECK-GI-NEXT: and w17, w17, #0x1
+; CHECK-GI-NEXT: orr w13, w13, w16, lsl #4
+; CHECK-GI-NEXT: and w14, w14, #0x1
+; CHECK-GI-NEXT: umov.b w0, v0[7]
+; CHECK-GI-NEXT: orr w8, w8, w10, lsl #2
+; CHECK-GI-NEXT: umov.b w10, v1[5]
+; CHECK-GI-NEXT: umov.b w16, v1[6]
+; CHECK-GI-NEXT: orr w13, w13, w17, lsl #5
+; CHECK-GI-NEXT: umov.b w17, v0[4]
+; CHECK-GI-NEXT: and w15, w15, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w14, lsl #3
+; CHECK-GI-NEXT: and w12, w12, #0x1
+; CHECK-GI-NEXT: and w11, w11, #0x1
+; CHECK-GI-NEXT: umov.b w14, v1[7]
+; CHECK-GI-NEXT: orr w9, w9, w12, lsl #3
+; CHECK-GI-NEXT: orr w11, w13, w11, lsl #6
+; CHECK-GI-NEXT: orr w8, w8, w15, lsl #4
+; CHECK-GI-NEXT: umov.b w15, v0[5]
+; CHECK-GI-NEXT: and w10, w10, #0x1
+; CHECK-GI-NEXT: and w0, w0, #0x1
+; CHECK-GI-NEXT: and w12, w17, #0x1
+; CHECK-GI-NEXT: umov.b w13, v0[1]
+; CHECK-GI-NEXT: orr w8, w8, w10, lsl #5
+; CHECK-GI-NEXT: and w16, w16, #0x1
+; CHECK-GI-NEXT: orr w9, w9, w12, lsl #4
+; CHECK-GI-NEXT: umov.b w10, v0[0]
+; CHECK-GI-NEXT: orr w11, w11, w0, lsl #7
+; CHECK-GI-NEXT: and w14, w14, #0x1
+; CHECK-GI-NEXT: and w12, w15, #0x1
+; CHECK-GI-NEXT: umov.b w15, v0[2]
+; CHECK-GI-NEXT: orr w8, w8, w16, lsl #6
+; CHECK-GI-NEXT: orr w9, w9, w12, lsl #5
+; CHECK-GI-NEXT: umov.b w12, v0[6]
+; CHECK-GI-NEXT: strb w11, [sp, #8]
+; CHECK-GI-NEXT: and w11, w13, #0x1
+; CHECK-GI-NEXT: umov.b w13, v0[3]
+; CHECK-GI-NEXT: orr w8, w8, w14, lsl #7
+; CHECK-GI-NEXT: umov.b w14, v0[7]
+; CHECK-GI-NEXT: ldr b0, [sp, #8]
+; CHECK-GI-NEXT: bfi w10, w11, #1, #31
+; CHECK-GI-NEXT: and w11, w15, #0x1
+; CHECK-GI-NEXT: strb w8, [sp, #9]
+; CHECK-GI-NEXT: umov.b w15, v0[4]
+; CHECK-GI-NEXT: and w8, w12, #0x1
+; CHECK-GI-NEXT: orr w10, w10, w11, lsl #2
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #6
+; CHECK-GI-NEXT: and w9, w13, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[1]
+; CHECK-GI-NEXT: orr w9, w10, w9, lsl #3
+; CHECK-GI-NEXT: umov.b w10, v0[5]
+; CHECK-GI-NEXT: umov.b w12, v0[0]
+; CHECK-GI-NEXT: and w13, w14, #0x1
+; CHECK-GI-NEXT: umov.b w16, v0[2]
+; CHECK-GI-NEXT: umov.b w17, v0[3]
+; CHECK-GI-NEXT: and w14, w15, #0x1
+; CHECK-GI-NEXT: umov.b w15, v0[2]
+; CHECK-GI-NEXT: orr w8, w8, w13, lsl #7
+; CHECK-GI-NEXT: orr w9, w9, w14, lsl #4
+; CHECK-GI-NEXT: umov.b w13, v0[6]
+; CHECK-GI-NEXT: and w11, w11, #0x1
+; CHECK-GI-NEXT: umov.b w14, v0[3]
+; CHECK-GI-NEXT: strb w8, [sp, #10]
+; CHECK-GI-NEXT: and w8, w10, #0x1
+; CHECK-GI-NEXT: bfi w12, w11, #1, #31
+; CHECK-GI-NEXT: orr w8, w9, w8, lsl #5
+; CHECK-GI-NEXT: umov.b w10, v0[4]
+; CHECK-GI-NEXT: and w9, w15, #0x1
+; CHECK-GI-NEXT: umov.b w11, v0[7]
+; CHECK-GI-NEXT: umov.b w15, v0[1]
+; CHECK-GI-NEXT: orr w9, w12, w9, lsl #2
+; CHECK-GI-NEXT: umov.b w12, v0[5]
+; CHECK-GI-NEXT: and w13, w13, #0x1
+; CHECK-GI-NEXT: and w14, w14, #0x1
+; CHECK-GI-NEXT: orr w8, w8, w13, lsl #6
+; CHECK-GI-NEXT: umov.b w13, v0[0]
+; CHECK-GI-NEXT: orr w9, w9, w14, lsl #3
+; CHECK-GI-NEXT: and w10, w10, #0x1
+; CHECK-GI-NEXT: umov.b w14, v0[6]
+; CHECK-GI-NEXT: and w11, w11, #0x1
+; CHECK-GI-NEXT: and w15, w15, #0x1
+; CHECK-GI-NEXT: umov.b w0, v0[3]
+; CHECK-GI-NEXT: orr w9, w9, w10, lsl #4
+; CHECK-GI-NEXT: and w10, w12, #0x1
+; CHECK-GI-NEXT: umov.b w12, v0[7]
+; CHECK-GI-NEXT: orr w8, w8, w11, lsl #7
+; CHECK-GI-NEXT: bfi w13, w15, #1, #31
+; CHECK-GI-NEXT: and w11, w16, #0x1
+; CHECK-GI-NEXT: orr w9, w9, w10, lsl #5
+; CHECK-GI-NEXT: and w10, w14, #0x1
+; CHECK-GI-NEXT: umov.b w14, v0[4]
+; CHECK-GI-NEXT: strb w8, [sp, #11]
+; CHECK-GI-NEXT: umov.b w15, v0[1]
+; CHECK-GI-NEXT: umov.b w16, v0[3]
+; CHECK-GI-NEXT: orr w8, w9, w10, lsl #6
+; CHECK-GI-NEXT: orr w9, w13, w11, lsl #2
+; CHECK-GI-NEXT: and w10, w12, #0x1
+; CHECK-GI-NEXT: and w11, w17, #0x1
+; CHECK-GI-NEXT: umov.b w12, v0[5]
+; CHECK-GI-NEXT: umov.b w17, v0[0]
+; CHECK-GI-NEXT: orr w8, w8, w10, lsl #7
+; CHECK-GI-NEXT: orr w9, w9, w11, lsl #3
+; CHECK-GI-NEXT: umov.b w10, v0[1]
+; CHECK-GI-NEXT: and w11, w14, #0x1
+; CHECK-GI-NEXT: umov.b w14, v0[0]
+; CHECK-GI-NEXT: and w15, w15, #0x1
+; CHECK-GI-NEXT: orr w9, w9, w11, lsl #4
+; CHECK-GI-NEXT: umov.b w11, v0[2]
+; CHECK-GI-NEXT: umov.b w13, v0[6]
+; CHECK-GI-NEXT: and w12, w12, #0x1
+; CHECK-GI-NEXT: bfi w17, w15, #1, #31
+; CHECK-GI-NEXT: umov.b w15, v0[5]
+; CHECK-GI-NEXT: orr w9, w9, w12, lsl #5
+; CHECK-GI-NEXT: and w10, w10, #0x1
+; CHECK-GI-NEXT: umov.b w12, v0[2]
+; CHECK-GI-NEXT: bfi w14, w10, #1, #31
+; CHECK-GI-NEXT: umov.b w10, v0[4]
+; CHECK-GI-NEXT: ldr b1, [sp, #9]
+; CHECK-GI-NEXT: and w11, w11, #0x1
+; CHECK-GI-NEXT: and w13, w13, #0x1
+; CHECK-GI-NEXT: strb w8, [sp, #12]
+; CHECK-GI-NEXT: orr w11, w14, w11, lsl #2
+; CHECK-GI-NEXT: and w14, w16, #0x1
+; CHECK-GI-NEXT: umov.b w16, v0[4]
+; CHECK-GI-NEXT: and w12, w12, #0x1
+; CHECK-GI-NEXT: and w15, w15, #0x1
+; CHECK-GI-NEXT: orr w9, w9, w13, lsl #6
+; CHECK-GI-NEXT: orr w11, w11, w14, lsl #3
+; CHECK-GI-NEXT: orr w12, w17, w12, lsl #2
+; CHECK-GI-NEXT: and w10, w10, #0x1
+; CHECK-GI-NEXT: and w17, w0, #0x1
+; CHECK-GI-NEXT: umov.b w0, v0[5]
+; CHECK-GI-NEXT: umov.b w14, v0[6]
+; CHECK-GI-NEXT: orr w10, w11, w10, lsl #4
+; CHECK-GI-NEXT: orr w12, w12, w17, lsl #3
+; CHECK-GI-NEXT: umov.b w11, v0[7]
+; CHECK-GI-NEXT: and w16, w16, #0x1
+; CHECK-GI-NEXT: umov.b w17, v0[6]
+; CHECK-GI-NEXT: orr w10, w10, w15, lsl #5
+; CHECK-GI-NEXT: umov.b w15, v0[7]
+; CHECK-GI-NEXT: orr w12, w12, w16, lsl #4
+; CHECK-GI-NEXT: and w16, w0, #0x1
+; CHECK-GI-NEXT: umov.b w0, v0[7]
+; CHECK-GI-NEXT: and w14, w14, #0x1
+; CHECK-GI-NEXT: orr w12, w12, w16, lsl #5
+; CHECK-GI-NEXT: orr w10, w10, w14, lsl #6
+; CHECK-GI-NEXT: and w11, w11, #0x1
+; CHECK-GI-NEXT: and w13, w17, #0x1
+; CHECK-GI-NEXT: orr w9, w9, w11, lsl #7
+; CHECK-GI-NEXT: mov.s v0[1], v1[0]
+; CHECK-GI-NEXT: orr w11, w12, w13, lsl #6
+; CHECK-GI-NEXT: and w12, w15, #0x1
+; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: orr w8, w10, w12, lsl #7
+; CHECK-GI-NEXT: and w10, w0, #0x1
+; CHECK-GI-NEXT: strb w9, [sp, #13]
+; CHECK-GI-NEXT: orr w9, w11, w10, lsl #7
+; CHECK-GI-NEXT: strb w8, [sp, #14]
+; CHECK-GI-NEXT: strb w9, [sp, #15]
+; CHECK-GI-NEXT: add sp, sp, #16
+; CHECK-GI-NEXT: ret
%bc = bitcast <16 x i1> %arg to <2 x i8>
ret <2 x i8> %bc
}
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