[llvm] 2c9dc08 - [AArch64] Use spill size when calculating callee saves size (NFC) (#123086)

[via llvm-commits]

Author: Benjamin Maxwell
Date: 2025-01-17T10:09:31Z
New Revision: 2c9dc089fd6aeb7570206b0a8b36cfb9298c2893

URL: https://github.com/llvm/llvm-project/commit/2c9dc089fd6aeb7570206b0a8b36cfb9298c2893
DIFF: https://github.com/llvm/llvm-project/commit/2c9dc089fd6aeb7570206b0a8b36cfb9298c2893.diff

LOG: [AArch64] Use spill size when calculating callee saves size (NFC) (#123086)

This is an NFC right now, as currently, all register and spill sizes are
the same, but the spill size is the correct size to use here.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 206e410047db56..dd248cf39a5ce9 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3795,14 +3795,15 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   unsigned CSStackSize = 0;
   unsigned SVECSStackSize = 0;
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
-  const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (unsigned Reg : SavedRegs.set_bits()) {
-    auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
+    auto *RC = TRI->getMinimalPhysRegClass(Reg);
+    assert(RC && "expected register class!");
+    auto SpillSize = TRI->getSpillSize(*RC);
     if (AArch64::PPRRegClass.contains(Reg) ||
         AArch64::ZPRRegClass.contains(Reg))
-      SVECSStackSize += RegSize;
+      SVECSStackSize += SpillSize;
     else
-      CSStackSize += RegSize;
+      CSStackSize += SpillSize;
   }
 
   // Increase the callee-saved stack size if the function has streaming mode