[llvm] [X86] Consistently use getVectorIdxConstant for element/subvector extract/insertion nodes. NFC. (PR #123312)
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Fri Jan 17 02:02:32 PST 2025
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git-clang-format --diff fbb9d49506baa05a613ab88f983d31e0f838dbae f0df35f61e7db8ebcdca627fa4ee2f4498eeb33c --extensions cpp -- llvm/lib/Target/X86/X86ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e5437eeebe..e4f8b1e16e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -9478,8 +9478,7 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG,
if ((NonZeros & (1 << i)) == 0)
continue;
- Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec,
- Op.getOperand(i),
+ Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(i),
DAG.getVectorIdxConstant(i * NumSubElems, dl));
}
@@ -9558,11 +9557,11 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
if (ResVT.getVectorNumElements() >= 16)
return Op; // The operation is legal with KUNPCK
- SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT,
- DAG.getUNDEF(ResVT), Op.getOperand(0),
- DAG.getVectorIdxConstant(0, dl));
+ SDValue Vec =
+ DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, DAG.getUNDEF(ResVT),
+ Op.getOperand(0), DAG.getVectorIdxConstant(0, dl));
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1),
- DAG.getVectorIdxConstant(NumElems/2, dl));
+ DAG.getVectorIdxConstant(NumElems / 2, dl));
}
static SDValue LowerCONCAT_VECTORS(SDValue Op,
@@ -17677,12 +17676,12 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
if ((int)Zeroable.countl_one() >= (NumElts - SubvecElts)) {
assert(Src >= 0 && "Expected a source!");
MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts);
- SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT,
- Src == 0 ? V1 : V2,
- DAG.getVectorIdxConstant(0, DL));
+ SDValue Extract =
+ DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT, Src == 0 ? V1 : V2,
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
- DAG.getConstant(0, DL, VT),
- Extract, DAG.getVectorIdxConstant(0, DL));
+ DAG.getConstant(0, DL, VT), Extract,
+ DAG.getVectorIdxConstant(0, DL));
}
// Try a simple shift right with undef elements. Later we'll try with zeros.
@@ -20623,8 +20622,8 @@ static SDValue LowerZERO_EXTEND_Mask(SDValue Op, const SDLoc &DL,
if (!ExtVT.is512BitVector() && !Subtarget.hasVLX()) {
NumElts *= 512 / ExtVT.getSizeInBits();
InVT = MVT::getVectorVT(MVT::i1, NumElts);
- In = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT, DAG.getUNDEF(InVT),
- In, DAG.getVectorIdxConstant(0, DL));
+ In = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT, DAG.getUNDEF(InVT), In,
+ DAG.getVectorIdxConstant(0, DL));
WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(),
NumElts);
}
@@ -24637,8 +24636,8 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue VSel = DAG.getSelect(DL, VecVT, VCmp, VOp1, VOp2);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
- VSel, DAG.getVectorIdxConstant(0, DL));
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, VSel,
+ DAG.getVectorIdxConstant(0, DL));
}
SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
@@ -24859,8 +24858,8 @@ static SDValue LowerSIGN_EXTEND_Mask(SDValue Op, const SDLoc &dl,
if (!ExtVT.is512BitVector() && !Subtarget.hasVLX()) {
NumElts *= 512 / ExtVT.getSizeInBits();
InVT = MVT::getVectorVT(MVT::i1, NumElts);
- In = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, InVT, DAG.getUNDEF(InVT),
- In, DAG.getVectorIdxConstant(0, dl));
+ In = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, InVT, DAG.getUNDEF(InVT), In,
+ DAG.getVectorIdxConstant(0, dl));
WideVT = MVT::getVectorVT(ExtVT.getVectorElementType(), NumElts);
}
@@ -26408,8 +26407,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
// Need to fill with zeros to ensure the bitcast will produce zeroes
// for the upper bits. An EXTRACT_ELEMENT here wouldn't guarantee that.
SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
- DAG.getConstant(0, dl, MVT::v8i1),
- CmpMask, DAG.getVectorIdxConstant(0, dl));
+ DAG.getConstant(0, dl, MVT::v8i1), CmpMask,
+ DAG.getVectorIdxConstant(0, dl));
return DAG.getBitcast(MVT::i8, Ins);
}
case COMI: { // Comparison intrinsics
@@ -26488,8 +26487,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
// Need to fill with zeros to ensure the bitcast will produce zeroes
// for the upper bits. An EXTRACT_ELEMENT here wouldn't guarantee that.
SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
- DAG.getConstant(0, dl, MVT::v16i1),
- FCmp, DAG.getVectorIdxConstant(0, dl));
+ DAG.getConstant(0, dl, MVT::v16i1), FCmp,
+ DAG.getVectorIdxConstant(0, dl));
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32,
DAG.getBitcast(MVT::i16, Ins));
}
@@ -50123,8 +50122,9 @@ static SDValue combineCompareEqual(SDNode *N, SelectionDAG &DAG,
SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
OnesOrZeroesF);
SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
- OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
- Vector32, DAG.getVectorIdxConstant(0, DL));
+ OnesOrZeroesF =
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Vector32,
+ DAG.getVectorIdxConstant(0, DL));
IntVT = MVT::i32;
}
``````````
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https://github.com/llvm/llvm-project/pull/123312
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