[clang] [llvm] [X86][AVX10.2-BF16] Update VCOMISBF16 intrinsics and instructions (PR #123307)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 17 01:22:50 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Phoebe Wang (phoebewang)
<details>
<summary>Changes</summary>
- Add `I` to intrinsics and instructions
- Add `_` before sbf16 in intrinsics
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
---
Patch is 31.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/123307.diff
14 Files Affected:
- (modified) clang/include/clang/Basic/BuiltinsX86.td (+6-6)
- (modified) clang/lib/Headers/avx10_2bf16intrin.h (+18-18)
- (modified) clang/test/CodeGen/X86/avx10_2bf16-builtins.c (+24-24)
- (modified) llvm/include/llvm/IR/IntrinsicsX86.td (+7-7)
- (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+7-7)
- (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (+6-6)
- (modified) llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll (+16-16)
- (modified) llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt (+14-14)
- (modified) llvm/test/MC/Disassembler/X86/avx10.2-bf16-64.txt (+14-14)
- (modified) llvm/test/MC/X86/avx10.2-bf16-32-att.s (+14-14)
- (modified) llvm/test/MC/X86/avx10.2-bf16-32-intel.s (+14-14)
- (modified) llvm/test/MC/X86/avx10.2-bf16-64-att.s (+14-14)
- (modified) llvm/test/MC/X86/avx10.2-bf16-64-intel.s (+14-14)
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+2-2)
``````````diff
diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index 18fc10eb85c027..312585fd6fc3b2 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -5376,12 +5376,12 @@ let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<
}
let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
- def vcomsbf16eq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
- def vcomsbf16lt : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
- def vcomsbf16neq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
- def vcomsbf16ge : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
- def vcomsbf16gt : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
- def vcomsbf16le : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
+ def vcomisbf16eq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
+ def vcomisbf16lt : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
+ def vcomisbf16neq : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
+ def vcomisbf16ge : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
+ def vcomisbf16gt : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
+ def vcomisbf16le : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
diff --git a/clang/lib/Headers/avx10_2bf16intrin.h b/clang/lib/Headers/avx10_2bf16intrin.h
index 0a427b9b7418b9..847c783825554f 100644
--- a/clang/lib/Headers/avx10_2bf16intrin.h
+++ b/clang/lib/Headers/avx10_2bf16intrin.h
@@ -523,34 +523,34 @@ _mm_maskz_min_pbh(__mmask8 __U, __m128bh __A, __m128bh __B) {
(__mmask8)__U, (__v8bf)_mm_min_pbh(__A, __B), (__v8bf)_mm_setzero_pbh());
}
-static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comeqsbh(__m128bh A,
- __m128bh B) {
- return __builtin_ia32_vcomsbf16eq((__v8bf)A, (__v8bf)B);
+static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comieq_sbh(__m128bh A,
+ __m128bh B) {
+ return __builtin_ia32_vcomisbf16eq((__v8bf)A, (__v8bf)B);
}
-static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comltsbh(__m128bh A,
- __m128bh B) {
- return __builtin_ia32_vcomsbf16lt((__v8bf)A, (__v8bf)B);
+static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comilt_sbh(__m128bh A,
+ __m128bh B) {
+ return __builtin_ia32_vcomisbf16lt((__v8bf)A, (__v8bf)B);
}
-static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comlesbh(__m128bh A,
- __m128bh B) {
- return __builtin_ia32_vcomsbf16le((__v8bf)A, (__v8bf)B);
+static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comile_sbh(__m128bh A,
+ __m128bh B) {
+ return __builtin_ia32_vcomisbf16le((__v8bf)A, (__v8bf)B);
}
-static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comgtsbh(__m128bh A,
- __m128bh B) {
- return __builtin_ia32_vcomsbf16gt((__v8bf)A, (__v8bf)B);
+static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comigt_sbh(__m128bh A,
+ __m128bh B) {
+ return __builtin_ia32_vcomisbf16gt((__v8bf)A, (__v8bf)B);
}
-static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comgesbh(__m128bh A,
- __m128bh B) {
- return __builtin_ia32_vcomsbf16ge((__v8bf)A, (__v8bf)B);
+static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comige_sbh(__m128bh A,
+ __m128bh B) {
+ return __builtin_ia32_vcomisbf16ge((__v8bf)A, (__v8bf)B);
}
-static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comneqsbh(__m128bh A,
- __m128bh B) {
- return __builtin_ia32_vcomsbf16neq((__v8bf)A, (__v8bf)B);
+static __inline__ int __DEFAULT_FN_ATTRS128 _mm_comineq_sbh(__m128bh A,
+ __m128bh B) {
+ return __builtin_ia32_vcomisbf16neq((__v8bf)A, (__v8bf)B);
}
#define _mm256_cmp_pbh_mask(__A, __B, __P) \
diff --git a/clang/test/CodeGen/X86/avx10_2bf16-builtins.c b/clang/test/CodeGen/X86/avx10_2bf16-builtins.c
index 9935137ca86775..f061b1d6cb8a39 100644
--- a/clang/test/CodeGen/X86/avx10_2bf16-builtins.c
+++ b/clang/test/CodeGen/X86/avx10_2bf16-builtins.c
@@ -648,40 +648,40 @@ __m128bh test_mm_maskz_min_pbh(__mmask16 __U, __m128bh __A, __m128bh __B) {
return _mm_maskz_min_pbh(__U, __A, __B);
}
-int test_mm_comeqsbh(__m128bh __A, __m128bh __B) {
- // CHECK-LABEL: test_mm_comeqsbh
- // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomsbf16eq(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
- return _mm_comeqsbh(__A, __B);
+int test_mm_comieq_sbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: test_mm_comieq_sbh
+ // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomisbf16eq(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
+ return _mm_comieq_sbh(__A, __B);
}
-int test_mm_comltsbh(__m128bh __A, __m128bh __B) {
- // CHECK-LABEL: test_mm_comltsbh
- // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomsbf16lt(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
- return _mm_comltsbh(__A, __B);
+int test_mm_comilt_sbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: test_mm_comilt_sbh
+ // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomisbf16lt(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
+ return _mm_comilt_sbh(__A, __B);
}
-int test_mm_comlesbh(__m128bh __A, __m128bh __B) {
- // CHECK-LABEL: test_mm_comlesbh
- // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomsbf16le(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
- return _mm_comlesbh(__A, __B);
+int test_mm_comile_sbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: test_mm_comile_sbh
+ // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomisbf16le(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
+ return _mm_comile_sbh(__A, __B);
}
-int test_mm_comgtsbh(__m128bh __A, __m128bh __B) {
- // CHECK-LABEL: test_mm_comgtsbh
- // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomsbf16gt(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
- return _mm_comgtsbh(__A, __B);
+int test_mm_comigt_sbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: test_mm_comigt_sbh
+ // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomisbf16gt(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
+ return _mm_comigt_sbh(__A, __B);
}
-int test_mm_comgesbh(__m128bh __A, __m128bh __B) {
- // CHECK-LABEL: test_mm_comgesbh
- // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomsbf16ge(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
- return _mm_comgesbh(__A, __B);
+int test_mm_comige_sbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: test_mm_comige_sbh
+ // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomisbf16ge(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
+ return _mm_comige_sbh(__A, __B);
}
-int test_mm_comneqsbh(__m128bh __A, __m128bh __B) {
- // CHECK-LABEL: test_mm_comneqsbh
- // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomsbf16neq(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
- return _mm_comneqsbh(__A, __B);
+int test_mm_comineq_sbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: test_mm_comineq_sbh
+ // CHECK: %{{.}} = call i32 @llvm.x86.avx10.vcomisbf16neq(<8 x bfloat> %{{.}}, <8 x bfloat> %{{.}})
+ return _mm_comineq_sbh(__A, __B);
}
__mmask16 test_mm256_cmp_pbh_mask_eq_oq(__m256bh a, __m256bh b) {
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 42b211e0e1f75a..6882444cc10fce 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -7642,22 +7642,22 @@ def int_x86_avx10_vminpbf16256 : ClangBuiltin<"__builtin_ia32_vminpbf16256">,
def int_x86_avx10_vminpbf16128 : ClangBuiltin<"__builtin_ia32_vminpbf16128">,
DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty],
[IntrNoMem]>;
-def int_x86_avx10_vcomsbf16eq : ClangBuiltin<"__builtin_ia32_vcomsbf16eq">,
+def int_x86_avx10_vcomisbf16eq : ClangBuiltin<"__builtin_ia32_vcomisbf16eq">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty],
[IntrNoMem]>;
-def int_x86_avx10_vcomsbf16lt : ClangBuiltin<"__builtin_ia32_vcomsbf16lt">,
+def int_x86_avx10_vcomisbf16lt : ClangBuiltin<"__builtin_ia32_vcomisbf16lt">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_v8bf16_ty,llvm_v8bf16_ty],
[IntrNoMem]>;
-def int_x86_avx10_vcomsbf16le : ClangBuiltin<"__builtin_ia32_vcomsbf16le">,
+def int_x86_avx10_vcomisbf16le : ClangBuiltin<"__builtin_ia32_vcomisbf16le">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty],
[IntrNoMem]>;
-def int_x86_avx10_vcomsbf16gt : ClangBuiltin<"__builtin_ia32_vcomsbf16gt">,
+def int_x86_avx10_vcomisbf16gt : ClangBuiltin<"__builtin_ia32_vcomisbf16gt">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty],
[IntrNoMem]>;
-def int_x86_avx10_vcomsbf16ge : ClangBuiltin<"__builtin_ia32_vcomsbf16ge">,
+def int_x86_avx10_vcomisbf16ge : ClangBuiltin<"__builtin_ia32_vcomisbf16ge">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty],
[IntrNoMem]>;
-def int_x86_avx10_vcomsbf16neq : ClangBuiltin<"__builtin_ia32_vcomsbf16neq">,
+def int_x86_avx10_vcomisbf16neq : ClangBuiltin<"__builtin_ia32_vcomisbf16neq">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty],
[IntrNoMem]>;
def int_x86_avx10_mask_rsqrt_nepbf16_128 : ClangBuiltin<"__builtin_ia32_vrsqrtpbf16128_mask">,
@@ -7893,4 +7893,4 @@ def int_x86_movrsdi : ClangBuiltin<"__builtin_ia32_movrsdi">,
[IntrReadMem]>;
def int_x86_prefetchrs : ClangBuiltin<"__builtin_ia32_prefetchrs">,
Intrinsic<[], [llvm_ptr_ty], []>;
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td
index edbcb17297603b..e7d17dbb604a4e 100644
--- a/llvm/lib/Target/X86/X86InstrAVX10.td
+++ b/llvm/lib/Target/X86/X86InstrAVX10.td
@@ -1359,19 +1359,19 @@ defm VMINPBF16 : avx10_fp_binopne_int_pbf16<0x5D, "vmin", SchedWriteFCmpSizes, 0
defm VMAXPBF16 : avx10_fp_binopne_int_pbf16<0x5F, "vmax", SchedWriteFCmpSizes, 0>;
}
-// VCOMSBF16
+// VCOMISBF16
let Uses = []<Register>, mayRaiseFPException = 0,
Defs = [EFLAGS], Predicates = [HasAVX10_2] in {
//TODO: Replace null_frag with X86fcmp to support lowering `fcmp oeq bfloat *`
//which may require extend supports on BFR16X, loadbf16, ...
- defm VCOMSBF16Z : sse12_ord_cmp<0x2F, FR16X, null_frag, bf16, f16mem, loadf16,
- "comsbf16", SSEPackedSingle>, T_MAP5, PD, EVEX,
- VEX_LIG, EVEX_CD8<16, CD8VT1>;
+ defm VCOMISBF16Z : sse12_ord_cmp<0x2F, FR16X, null_frag, bf16, f16mem, loadf16,
+ "comisbf16", SSEPackedSingle>, T_MAP5, PD, EVEX,
+ VEX_LIG, EVEX_CD8<16, CD8VT1>;
let isCodeGenOnly = 1 in {
- defm VCOMSBF16Z : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v8bf16, f16mem,
- sse_load_bf16, "comsbf16", SSEPackedSingle>,
- T_MAP5, PD, EVEX, VEX_LIG, EVEX_CD8<16, CD8VT1>;
+ defm VCOMISBF16Z : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v8bf16, f16mem,
+ sse_load_bf16, "comisbf16", SSEPackedSingle>,
+ T_MAP5, PD, EVEX, VEX_LIG, EVEX_CD8<16, CD8VT1>;
}
}
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 86fd04046d16a0..ff0c0de9cde098 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -751,12 +751,12 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::FADD_RND),
X86_INTRINSIC_DATA(avx10_vaddps256, INTR_TYPE_2OP, ISD::FADD,
X86ISD::FADD_RND),
- X86_INTRINSIC_DATA(avx10_vcomsbf16eq, COMI, X86ISD::COMI, ISD::SETEQ),
- X86_INTRINSIC_DATA(avx10_vcomsbf16ge, COMI, X86ISD::COMI, ISD::SETGE),
- X86_INTRINSIC_DATA(avx10_vcomsbf16gt, COMI, X86ISD::COMI, ISD::SETGT),
- X86_INTRINSIC_DATA(avx10_vcomsbf16le, COMI, X86ISD::COMI, ISD::SETLE),
- X86_INTRINSIC_DATA(avx10_vcomsbf16lt, COMI, X86ISD::COMI, ISD::SETLT),
- X86_INTRINSIC_DATA(avx10_vcomsbf16neq, COMI, X86ISD::COMI, ISD::SETNE),
+ X86_INTRINSIC_DATA(avx10_vcomisbf16eq, COMI, X86ISD::COMI, ISD::SETEQ),
+ X86_INTRINSIC_DATA(avx10_vcomisbf16ge, COMI, X86ISD::COMI, ISD::SETGE),
+ X86_INTRINSIC_DATA(avx10_vcomisbf16gt, COMI, X86ISD::COMI, ISD::SETGT),
+ X86_INTRINSIC_DATA(avx10_vcomisbf16le, COMI, X86ISD::COMI, ISD::SETLE),
+ X86_INTRINSIC_DATA(avx10_vcomisbf16lt, COMI, X86ISD::COMI, ISD::SETLT),
+ X86_INTRINSIC_DATA(avx10_vcomisbf16neq, COMI, X86ISD::COMI, ISD::SETNE),
X86_INTRINSIC_DATA(avx10_vcvtne2ph2bf8128, INTR_TYPE_2OP,
X86ISD::VCVTNE2PH2BF8, 0),
X86_INTRINSIC_DATA(avx10_vcvtne2ph2bf8256, INTR_TYPE_2OP,
diff --git a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
index 59151d4dd96099..6dd86d9afef969 100644
--- a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll
@@ -118,23 +118,23 @@ define <8 x bfloat> @test_int_x86_avx10_maskz_max_nepbf16_128(<8 x bfloat> %x1,
ret <8 x bfloat> %res1
}
-declare i32 @llvm.x86.avx10.vcomsbf16eq(<8 x bfloat>, <8 x bfloat>)
-declare i32 @llvm.x86.avx10.vcomsbf16lt(<8 x bfloat>, <8 x bfloat>)
-declare i32 @llvm.x86.avx10.vcomsbf16le(<8 x bfloat>, <8 x bfloat>)
-declare i32 @llvm.x86.avx10.vcomsbf16gt(<8 x bfloat>, <8 x bfloat>)
-declare i32 @llvm.x86.avx10.vcomsbf16ge(<8 x bfloat>, <8 x bfloat>)
-declare i32 @llvm.x86.avx10.vcomsbf16neq(<8 x bfloat>, <8 x bfloat>)
+declare i32 @llvm.x86.avx10.vcomisbf16eq(<8 x bfloat>, <8 x bfloat>)
+declare i32 @llvm.x86.avx10.vcomisbf16lt(<8 x bfloat>, <8 x bfloat>)
+declare i32 @llvm.x86.avx10.vcomisbf16le(<8 x bfloat>, <8 x bfloat>)
+declare i32 @llvm.x86.avx10.vcomisbf16gt(<8 x bfloat>, <8 x bfloat>)
+declare i32 @llvm.x86.avx10.vcomisbf16ge(<8 x bfloat>, <8 x bfloat>)
+declare i32 @llvm.x86.avx10.vcomisbf16neq(<8 x bfloat>, <8 x bfloat>)
define i32 @test_x86_avx10_com_nesbf16_eq(<8 x bfloat> %a0, <8 x bfloat> %a1) {
; CHECK-LABEL: test_x86_avx10_com_nesbf16_eq:
; CHECK: # %bb.0:
-; CHECK-NEXT: vcomsbf16 %xmm1, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc1]
+; CHECK-NEXT: vcomisbf16 %xmm1, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc1]
; CHECK-NEXT: setnp %al # encoding: [0x0f,0x9b,0xc0]
; CHECK-NEXT: sete %cl # encoding: [0x0f,0x94,0xc1]
; CHECK-NEXT: andb %al, %cl # encoding: [0x20,0xc1]
; CHECK-NEXT: movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call i32 @llvm.x86.avx10.vcomsbf16eq(<8 x bfloat> %a0, <8 x bfloat> %a1)
+ %res = call i32 @llvm.x86.avx10.vcomisbf16eq(<8 x bfloat> %a0, <8 x bfloat> %a1)
ret i32 %res
}
@@ -142,10 +142,10 @@ define i32 @test_x86_avx10_com_nesbf16_lt(<8 x bfloat> %a0, <8 x bfloat> %a1) {
; CHECK-LABEL: test_x86_avx10_com_nesbf16_lt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: vcomsbf16 %xmm0, %xmm1 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc8]
+; CHECK-NEXT: vcomisbf16 %xmm0, %xmm1 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc8]
; CHECK-NEXT: seta %al # encoding: [0x0f,0x97,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call i32 @llvm.x86.avx10.vcomsbf16lt(<8 x bfloat> %a0, <8 x bfloat> %a1)
+ %res = call i32 @llvm.x86.avx10.vcomisbf16lt(<8 x bfloat> %a0, <8 x bfloat> %a1)
ret i32 %res
}
@@ -153,10 +153,10 @@ define i32 @test_x86_avx10_com_nesbf16_le(<8 x bfloat> %a0, <8 x bfloat> %a1) {
; CHECK-LABEL: test_x86_avx10_com_nesbf16_le:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: vcomsbf16 %xmm0, %xmm1 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc8]
+; CHECK-NEXT: vcomisbf16 %xmm0, %xmm1 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc8]
; CHECK-NEXT: setae %al # encoding: [0x0f,0x93,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call i32 @llvm.x86.avx10.vcomsbf16le(<8 x bfloat> %a0, <8 x bfloat> %a1)
+ %res = call i32 @llvm.x86.avx10.vcomisbf16le(<8 x bfloat> %a0, <8 x bfloat> %a1)
ret i32 %res
}
@@ -164,23 +164,23 @@ define i32 @test_x86_avx10_com_nesbf16_gt(<8 x bfloat> %a0, <8 x bfloat> %a1) {
; CHECK-LABEL: test_x86_avx10_com_nesbf16_gt:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: vcomsbf16 %xmm1, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc1]
+; CHECK-NEXT: vcomisbf16 %xmm1, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc1]
; CHECK-NEXT: setae %al # encoding: [0x0f,0x93,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call i32 @llvm.x86.avx10.vcomsbf16ge(<8 x bfloat> %a0, <8 x bfloat> %a1)
+ %res = call i32 @llvm.x86.avx10.vcomisbf16ge(<8 x bfloat> %a0, <8 x bfloat> %a1)
ret i32 %res
}
define i32 @test_x86_avx10_com_nesbf16_neq(<8 x bfloat> %a0, <8 x bfloat> %a1) {
; CHECK-LABEL: test_x86_avx10_com_nesbf16_neq:
; CHECK: # %bb.0:
-; CHECK-NEXT: vcomsbf16 %xmm1, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc1]
+; CHECK-NEXT: vcomisbf16 %xmm1, %xmm0 # encoding: [0x62,0xf5,0x7d,0x08,0x2f,0xc1]
; CHECK-NEXT: setp %al # encoding: [0x0f,0x9a,0xc0]
; CHECK-NEXT: setne %cl # encoding: [0x0f,0x95,0xc1]
; CHECK-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
; CHECK-NEXT: movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call i32 @llvm.x86.avx10.vcomsbf16neq(<8 x bfloat> %a0, <8 x bfloat> %a1)
+ %res = call i32 @llvm.x86.avx10.vcomisbf16neq(<8 x bfloat> %a0, <8 x bfloat> %a1)
ret i32 %res
}
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt b/llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
index 8cc53db077e4f7..ea64ef1419a15d 100644
--- a/llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
+++ b/llvm/test/MC/Disassembler/X86/avx10.2-bf16-32.txt
@@ -205,32 +205,32 @@
# INTEL: vcmppbf16 k5 {k7}, ymm3, word ptr [edx - 256]{1to16}, 123
0x62,0xf3,0x67,0x3f,0xc2,0x6a,0x80,0x7b
-# ATT: vcomsbf16 %xmm3, %xmm2
-# INTEL: vcomsbf16 xmm2, xmm3
+# ATT: vcomisbf16 %xmm3, %xmm2
+# INTEL: vcomisbf16 xmm2, xmm3
0x62,0xf5,0x7d,0x08,0x2f,0xd3
-# ATT: vcomsbf16 268435456(%esp,%esi,8), %xmm2
-# INTEL: vcomsbf16 xmm2, word ptr [esp + 8*esi + 268435456]
+# ATT: vcomisbf16 268435456(%esp,%esi,8), %xmm2
+# INTEL: vcomisbf16 xmm2, word ptr [esp + 8*esi + 268435456]
0x62,0xf5,0x7d,0x08,0x2f,0x94,0xf4,0x00,0x00,0x00,0x10
-# ATT: vcomsbf16 291(%edi,%eax,4), %xmm2
-# INTEL: vcomsbf16 xmm2, word ptr [edi + 4*eax + 291]
+# ATT: vcomisbf16 291(%edi,%eax,4), %xmm2
+# INTEL: vcomisbf16 xmm2, word ptr [edi + 4*eax + 291]
0x62,0xf5,0x7d,0x08,0x2f,0x94,0x87,0x23,0x01,0x00,0x00
-# ATT: vcomsbf16 (%eax), %xmm2
-# INTEL: vcomsbf16 xmm2, word ptr [eax]
+# ATT: vcomisbf16 (%eax), %xmm2
+# INTEL: vcomisbf16 xmm2, word ptr [eax]
0x62,0xf5,0x7d,0x08,0x2f,0x10
-# ATT: vcomsbf16 -64(,%ebp,2), %xmm2
-# INTEL: vcomsbf16 xmm2, word ptr [2*ebp - 64]
+# ATT: vcomisbf16 -64(,%ebp,2), %xmm2
+# INTEL: vcomisbf16 xmm2, word ptr [2*ebp - 64]
0x62,0xf5,0x7d,0x08,0x2f,0x14,0x6d,0xc0,0xff,0xff,0xff
-# ATT: vcomsbf16 254(%ecx), %xmm2
-# INTEL: vcomsbf16 xmm2, word ptr [ecx + 254]
+# ATT: vcomisbf16 254(%ecx), %xmm2
+# INTEL: vcomisbf16 xmm2, word ptr [ecx + 254]
0x62,0xf5,0x7d,0x08,0x2f,0x51,0x7f
-# ATT: vcomsbf16 -256(%edx), %xmm2
-# INTEL: vcomsbf16 xmm2, word ptr [edx - 256]
+# ATT: vcomisbf16 -256(%edx), %xmm2
+# INTEL: vcomisbf16 xmm2, word ptr [edx - 256]
0x62,0xf5,0x7d,0x08,0x2f,0x52,0x80
# ATT: vdivnepbf16 %ymm4, %ymm3, %ymm2
diff --git a/...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/123307
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