[llvm] [DAGCombiner] Fix scalarizeExtractedBinOp for some SETCC cases (PR #123071)

[David Sherwood via llvm-commits]

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@@ -22808,9 +22808,26 @@ static SDValue scalarizeExtractedBinOp(SDNode *ExtElt, SelectionDAG &DAG,
     return SDValue();
 
   EVT ResVT = ExtElt->getValueType(0);
-  if (Opc == ISD::SETCC &&
-      (ResVT != Vec.getValueType().getVectorElementType() || LegalTypes))
-    return SDValue();
+  bool SetCCNeedsSignExt = false;
+  if (Opc == ISD::SETCC) {
+    EVT VecVT = Vec.getValueType();
+    if (ResVT != VecVT.getVectorElementType() || LegalTypes)
+      return SDValue();
+
+    if (ResVT != MVT::i1) {
+      bool VecRequiresSignExt = TLI.getBooleanContents(VecVT) ==
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david-arm wrote:

Yeah I originally did that, but it's impossible to write a test case for the and (zext-in-reg) so the code will remain undefended. At least I couldn't find a target that exhibited that behaviour. I thought perhaps in this case it was better to bail out until a target required it? Having said that, I'm happy to support the case if we believe that testing isn't required.

https://github.com/llvm/llvm-project/pull/123071