[llvm] selecting v_sat_pk instruction, version 2 (PR #123297)

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git-clang-format --diff e8999309f16a248cb14ac09bc1f256cbf202f475 5844fd43354c99d8319118e2463f8c55f0ec0058 --extensions cpp,h -- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 58361b1e63..0f92c0f1d5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -868,12 +868,14 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   // special dealing for v_sat_pk instruction
   if (AMDGPU::isGFX9(STI) || AMDGPU::isGFX11(STI) || AMDGPU::isGFX12(STI)) {
     // In foldToSaturated during DAG combine
-    // 1. isOperationLegalOrCustom(Opc, SrcVT) getOperationAction(Op, SrcVT) == Custom
-    // 2. isTypeDesirableForOp checks regclass for v2i8 (hooked now checking DstVT == v2i8)
-    // In CustomLowerNode during legalizing, checks getOperationAction(Op, DstVT) == Custom
+    // 1. isOperationLegalOrCustom(Opc, SrcVT) getOperationAction(Op, SrcVT) ==
+    // Custom
+    // 2. isTypeDesirableForOp checks regclass for v2i8 (hooked now checking
+    // DstVT == v2i8) In CustomLowerNode during legalizing, checks
+    // getOperationAction(Op, DstVT) == Custom
     setOperationAction(ISD::TRUNCATE_SSAT_U, {MVT::v2i16, MVT::v2i8}, Custom);
   }
-  
+
   setOperationAction(ISD::INTRINSIC_WO_CHAIN,
                      {MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16,
                       MVT::bf16, MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::i128,
@@ -1983,8 +1985,8 @@ bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
   // create setcc with i1 operands.  We don't have instructions for i1 setcc.
   if (VT == MVT::i1 && Op == ISD::SETCC)
     return false;
-  
-  // Avoiding legality check for reg type of v2i8 
+
+  // Avoiding legality check for reg type of v2i8
   // (do not need to addRegisterClass for v2i8)
   // VT is result type, ensure the result type is v2i8
   if (VT == MVT::v2i8 && Op == ISD::TRUNCATE_SSAT_U)
@@ -6622,7 +6624,8 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
   }
   case ISD::TRUNCATE_SSAT_U: {
     SDLoc SL(N);
-    SDValue Op = DAG.getNode(AMDGPUISD::SAT_PK_CAST, SL, MVT::i16, N->getOperand(0));
+    SDValue Op =
+        DAG.getNode(AMDGPUISD::SAT_PK_CAST, SL, MVT::i16, N->getOperand(0));
     Results.push_back(Op);
     break;
   }

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https://github.com/llvm/llvm-project/pull/123297