[llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)

[Craig Topper via llvm-commits]

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+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Base P'
+// Packed SIMD instruction set extension.
+///
+/// This version is still experimental as the 'P' extension hasn't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def simm10 : RISCVSImmLeafOp<10> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (MCOp.evaluateAsConstantImm(Imm))
+      return isInt<10>(Imm);
+    return MCOp.isBareSymbolRef();
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnary<bits<5> funct5, bits<7> wuimm,
+               bits<3> funct3, RISCVOpcode opcode,
+               string opcodestr>
+    : RVInstIBase<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
+                  opcodestr, "$rd, $rs1"> {
+    let Inst{31-27} = funct5;
+    let Inst{26-20} = wuimm;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9<bits<7> funct7, RISCVOpcode opcode,
+                                 string opcodestr, DAGOperand TyRd = GPR>
+  : RVInstIBase<0b010, opcode, (outs TyRd:$rd), (ins simm10:$simm10),
+                opcodestr, "$rd, $simm10"> {
+  bits<10> simm10;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-15} = simm10;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm8<bits<8> funct8, RISCVOpcode opcode,
+                                 string opcodestr, DAGOperand TyRd = GPR>
+  : RVInstIBase<0b010, opcode, (outs TyRd:$rd), (ins uimm8:$uimm8),
+                opcodestr, "$rd, $uimm8"> {
+  bits<8> uimm8;
+  let Inst{31-24} = funct8;
+  let Inst{23-16} = uimm8;
+  let Inst{15} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUF<bits<2> w, bits<5> uf,
+               string opcodestr>
+    : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
+                        opcodestr, "$rd, $rs1">  {
+  let Inst{31-27} = 0b11100;
+  let Inst{26-25} = w;
+  let Inst{24-20} = uf;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUFRs1pRdp<bits<2> w, bits<5> uf, string opcodestr>
+    : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPRPairRV32:$rdp), (ins GPRPairRV32:$rs1p),
+                        opcodestr, "$rdp, $rs1p">  {
+  bits<4> rs1p;
+  bits<4> rdp;
+
+  let Inst{31-27} = 0b01100;
+  let Inst{26-25} = w;
+  let Inst{24-20} = uf;
+  let Inst{19-16} = rs1p;
+  let Inst{15}    = 0b0;
+  let Inst{11-8}  = rdp;
+  let Inst{7}     = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryF<bit bfr, bits<3> f, bit aft, bits<7> wuimm,
+                string opcodestr, bits<3> funct3 = 0b100,
+                dag outs = (outs GPR:$rd), dag ins = (ins GPR:$rs1),
+                string argstr = "$rd, $rs1">
+    : RVInstIBase<funct3, OPC_OP_IMM_32, outs, ins, opcodestr, argstr>  {
+  let Inst{31} = bfr;
+  let Inst{30-28} = f;
+  let Inst{27} = aft;
+  let Inst{26-20} = wuimm;
+}
+
+class RVPUnary1F0<bits<3> f, bits<7> wuimm, string opcodestr>
+    : RVPUnaryF<1, f, 0, wuimm, opcodestr>;
+
+class RVPUnary0F0Rdp<bits<3> f, bits<7> wuimm, string opcodestr>
+    : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b100, (outs GPRPairRV32:$rdp),
+               (ins GPR:$rs1), "$rdp, $rs1"> {
+  bits<4> rdp;
+
+  let Inst{11-8} = rdp;
+  let Inst{7}    = 0b0;
+}
+
+class RVPUnary0F0Rs1p<bits<3> f, bits<7> wuimm, string opcodestr>
+    : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b100, (outs GPR:$rd),
+               (ins GPRPairRV32:$rs1p), "$rd, $rs1p"> {
+  bits<4> rs1p;
+
+  let Inst{19-16} = rs1p;
+  let Inst{15}    = 0b1;
+}
+
+class RVPUnary0F0Rs1pRdp<bits<3> f, bits<7> wuimm, string opcodestr,
+                         bit aft = 0b0>
+    : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b100, (outs GPRPairRV32:$rdp),
+               (ins GPRPairRV32:$rs1p), "$rdp, $rs1p"> {
+  bits<4> rs1p;
+  bits<4> rdp;
+
+  let Inst{19-16} = rs1p;
+  let Inst{15}    = aft;
+  let Inst{11-8}  = rdp;
+  let Inst{7}     = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinaryFW<bit bfr, bits<3> f, bit aft, bits<2> w,
+               string opcodestr, bits<3> funct3, RISCVOpcode Opcode = OPC_OP_32,
----------------
topperc wrote:

Indent 3 more spaces

https://github.com/llvm/llvm-project/pull/123271