[llvm] [LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT (PR #122863)

[Lu Weining via llvm-commits]

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@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+;; Test scalar_to_vector expansion.
+
+define <16 x i8> @scalar_to_16xi8(i8 %val) {
+; CHECK-LABEL: scalar_to_16xi8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT:    ret
+  %ret = insertelement <16 x i8> poison, i8 %val, i32 0
+  ret <16 x i8> %ret
+}
+
+define <8 x i16> @scalar_to_8xi16(i16 %val) {
+; CHECK-LABEL: scalar_to_8xi16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT:    ret
+  %ret = insertelement <8 x i16> poison, i16 %val, i32 0
+  ret <8 x i16> %ret
+}
+
+define <4 x i32> @scalar_to_4xi32(i32 %val) {
+; CHECK-LABEL: scalar_to_4xi32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT:    ret
+  %ret = insertelement <4 x i32> poison, i32 %val, i32 0
+  ret <4 x i32> %ret
+}
+
+define <2 x i64> @scalar_to_2xi64(i64 %val) {
+; CHECK-LABEL: scalar_to_2xi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vinsgr2vr.d $vr0, $a0, 0
+; CHECK-NEXT:    ret
+  %ret = insertelement <2 x i64> poison, i64 %val, i32 0
+  ret <2 x i64> %ret
+}
+
+define <4 x float> @scalar_to_4xf32(float %val) {
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SixWeining wrote:

Seems these could be `empty` because FR overlap with the lower part of the SIMD register.

https://github.com/llvm/llvm-project/pull/122863