[llvm] ReduxWidth check for 0 (PR #123257)

[George Chaltas via llvm-commits]

https://github.com/gchaltas created https://github.com/llvm/llvm-project/pull/123257

Added assert to check for underflow of ReduxWidth

	modified:   llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp


Source code analysis flagged   the operation (ReduxWwidth - 1) as potential underflow, since ReduxWidth is unsigned.
Realize that this should never happen if everything is working right, but added an assert to check for it just in case.

>From 071217c0610373b7b21aeacfe4cb264743eca928 Mon Sep 17 00:00:00 2001
From: George Chaltas <george.chaltas at intel.com>
Date: Thu, 16 Jan 2025 12:22:59 -0800
Subject: [PATCH] ReduxWidth check for 0

Added assert to check for underflow of ReduxWidth

	modified:   llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index b0b8f8249d657b..ae08b0e5a33403 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -20080,6 +20080,7 @@ class HorizontalReduction {
         NumRegs =
             TTI.getNumberOfRegisters(TTI.getRegisterClassForType(true, Tp));
         while (NumParts > NumRegs) {
+	  assert(ReduxWidth > 0 && "ReduxWidth is unexpectedly 0.");
           ReduxWidth = bit_floor(ReduxWidth - 1);
           VectorType *Tp = getWidenedType(ScalarTy, ReduxWidth);
           NumParts = TTI.getNumberOfParts(Tp);