[llvm] [AMDGPU][True16][MC] true16 for v_cmpx_class_f16 (PR #123251)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 16 14:54:24 PST 2025
https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/123251
None
>From af0e595efbe7882e6217e9147bbd88965bd443eb Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 14 Jan 2025 18:56:47 -0500
Subject: [PATCH] true16 for v_cmpx_class_f16
---
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 68 ++++++++++++-----
.../AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s | 65 +++++++++-------
.../AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s | 21 ++++--
.../MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s | 29 ++++---
llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s | 75 +++++++++++--------
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s | 65 +++++++++-------
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s | 21 ++++--
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s | 42 ++++++++---
.../MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s | 42 ++++++++---
llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s | 25 +++++--
llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s | 73 ++++++++++--------
llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s | 29 ++++---
llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s | 72 ++++++++++--------
llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s | 62 ++++++++-------
llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s | 18 +++--
llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s | 42 ++++++++---
.../MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s | 42 ++++++++---
.../gfx11_dasm_vop3_dpp16_from_vopcx.txt | 9 +++
.../gfx11_dasm_vop3_dpp8_from_vopcx.txt | 9 +++
.../AMDGPU/gfx11_dasm_vop3_from_vopcx.txt | 9 +++
.../Disassembler/AMDGPU/gfx11_dasm_vopcx.txt | 30 ++++++++
.../AMDGPU/gfx11_dasm_vopcx_dpp16.txt | 18 +++++
.../AMDGPU/gfx11_dasm_vopcx_dpp8.txt | 18 +++++
.../Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt | 20 +++++
.../AMDGPU/gfx12_dasm_vop3cx_dpp16.txt | 66 ++++++++++++++++
.../AMDGPU/gfx12_dasm_vop3cx_dpp8.txt | 9 +++
.../Disassembler/AMDGPU/gfx12_dasm_vopcx.txt | 24 ++++++
.../AMDGPU/gfx12_dasm_vopcx_dpp16.txt | 12 +++
.../AMDGPU/gfx12_dasm_vopcx_dpp8.txt | 12 +++
29 files changed, 740 insertions(+), 287 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 14e34c9e00ec6f..2616ab8ac411fd 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -905,41 +905,69 @@ multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> {
}
class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> :
- VOPC_Class_Profile<sched, src0VT, src1VT> {
+ VOPC_Class_Profile_Base<sched, src0VT, src1VT> {
let Outs64 = (outs );
let OutsSDWA = (outs );
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
src0_sel:$src0_sel, src1_sel:$src1_sel);
- let AsmVOP3Base = "$src0_modifiers, $src1";
+ let HasDst = 0;
let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
let EmitDst = 0;
}
multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> {
def NAME : VOPC_Class_NoSdst_Profile<sched, f16>;
- def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> {
+ def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, f16> {
let IsTrue16 = 1;
let IsRealTrue16 = 1;
- let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
- let Src1RC64 = VSrc_b32;
- let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
- let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
- let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
- let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
- let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
- let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
+ let HasOpSel = 1;
+ let HasModifiers = 1; // All instructions at least have OpSel
+ let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
+ let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;
+ let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;
+ let Src0VOP3DPP = VGPRSrc_16;
+ let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
+ let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
+
+ let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret;
+ let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret;
+ let Src2RC64 = getVOP3SrcForVT<Src2VT, 1/*IsTrue16*/>.ret;
+ let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
+ let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
+ let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 0/*IsFake16*/>.ret;
+ let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 0/*IsFake16*/>.ret;
}
- def _fake16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> {
+ def _fake16 : VOPC_Class_NoSdst_Profile<sched, f16, f16> {
let IsTrue16 = 1;
+ let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
- let Src1RC64 = VSrc_b32;
let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
- let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
- let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
- let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
+ let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
+ let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;
+ let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;
+ let Src0VOP3DPP = VGPRSrc_32;
+ let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
+ let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
+
+ let Src0RC64 = getVOP3SrcForVT<Src0VT, 0/*IsTrue16*/>.ret;
+ let Src1RC64 = getVOP3SrcForVT<Src1VT, 0/*IsTrue16*/>.ret;
+ let Src2RC64 = getVOP3SrcForVT<Src2VT, 0/*IsTrue16*/>.ret;
+ let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
+ let Src1Mod = getSrcMod<Src1VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret;
+ let Src2Mod = getSrcMod<Src2VT, 0/*IsTrue16*/, 1/*IsFake16*/>.ret;
+ let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret;
+ let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 1/*IsFake16*/>.ret;
+ let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 1/*IsFake16*/>.ret;
}
}
@@ -1761,6 +1789,12 @@ multiclass VOPCX_Real_t16_gfx11_gfx12<bits<9> op, string asm_name,
VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>,
VOPCX_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>;
+multiclass VOPCX_Real_t16_and_fake16_gfx11_gfx12<bits<9> op, string asm_name,
+ string OpName = NAME, string pseudo_mnemonic = ""> {
+ defm _t16: VOPCX_Real_t16_gfx11_gfx12<op, asm_name, OpName#"_t16", pseudo_mnemonic>;
+ defm _fake16: VOPCX_Real_t16_gfx11_gfx12<op, asm_name, OpName#"_fake16", pseudo_mnemonic>;
+}
+
defm V_CMP_F_F16_fake16 : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">;
defm V_CMP_LT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x001, "v_cmp_lt_f16">;
defm V_CMP_EQ_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x002, "v_cmp_eq_f16">;
@@ -1944,7 +1978,7 @@ defm V_CMPX_GT_U64 : VOPCX_Real_gfx11_gfx12<0x0dc>;
defm V_CMPX_NE_U64 : VOPCX_Real_gfx11_gfx12<0x0dd>;
defm V_CMPX_GE_U64 : VOPCX_Real_gfx11_gfx12<0x0de>;
defm V_CMPX_T_U64 : VOPCX_Real_gfx11<0x0df>;
-defm V_CMPX_CLASS_F16_fake16 : VOPCX_Real_t16_gfx11_gfx12<0x0fd, "v_cmpx_class_f16">;
+defm V_CMPX_CLASS_F16 : VOPCX_Real_t16_and_fake16_gfx11_gfx12<0x0fd, "v_cmpx_class_f16">;
defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11_gfx12<0x0fe>;
defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11_gfx12<0x0ff>;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
index 462ad7ba6516d5..0078878860d4f8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
@@ -3,47 +3,56 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_mirror
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_mirror
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_half_mirror
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_half_mirror
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shl:1
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:1
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shl:15
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:15
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shr:1
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:1
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shr:15
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:15
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_ror:1
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:1
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_ror:15
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:15
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
-v_cmpx_class_f16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
-v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.h row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: [0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: [0x7e,0x08,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: [0x7e,0x11,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
index 46f1db837b0dd8..d46ffd1b73a8a1 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
@@ -2,14 +2,23 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7e,0x01,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7e,0x01,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: [0x7e,0x08,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: [0x7e,0x11,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
index 371d29f2a2cb63..2a45bdfc0f9351 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
@@ -2,17 +2,17 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_cmpx_class_f16_e64 v1, v2
-// GFX11: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+v_cmpx_class_f16_e64 v1.l, v2.l
+// GFX11: v_cmpx_class_f16_e64 v1.l, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
-v_cmpx_class_f16_e64 v255, v2
-// GFX11: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+v_cmpx_class_f16_e64 v255.l, v2.l
+// GFX11: v_cmpx_class_f16_e64 v255.l, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
-v_cmpx_class_f16_e64 s1, v2
-// GFX11: v_cmpx_class_f16_e64 s1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+v_cmpx_class_f16_e64 s1, v2.l
+// GFX11: v_cmpx_class_f16_e64 s1, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
-v_cmpx_class_f16_e64 s105, v255
-// GFX11: v_cmpx_class_f16_e64 s105, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+v_cmpx_class_f16_e64 s105, v255.l
+// GFX11: v_cmpx_class_f16_e64 s105, v255.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
v_cmpx_class_f16_e64 vcc_lo, s2
// GFX11: v_cmpx_class_f16_e64 vcc_lo, s2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00]
@@ -47,8 +47,17 @@ v_cmpx_class_f16_e64 src_scc, vcc_lo
v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi
// GFX11: v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi ; encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
-v_cmpx_class_f16_e64 v1, 0.5
-// GFX11: v_cmpx_class_f16_e64 v1, 0.5 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+v_cmpx_class_f16_e64 v1.l, 0.5
+// GFX11: v_cmpx_class_f16_e64 v1.l, 0.5 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f16_e64 v1.h, v2.h
+// GFX11: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 v255.h, v2.l
+// GFX11: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s105, v255.h
+// GFX11: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
v_cmpx_class_f32_e64 v1, v2
// GFX11: v_cmpx_class_f32_e64 v1, v2 ; encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
index 82c43e1a91b6a8..da1db52a8721c8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
@@ -2,50 +2,65 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_cmpx_class_f16_e32 v1, v2
-// GFX11: v_cmpx_class_f16_e32 v1, v2 ; encoding: [0x01,0x05,0xfa,0x7d]
+v_cmpx_class_f16 v1.l, v2.l
+// GFX11: v_cmpx_class_f16_e32 v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7d]
-v_cmpx_class_f16 v127, v2
-// GFX11: v_cmpx_class_f16_e32 v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7d]
+v_cmpx_class_f16 v127.l, v2.l
+// GFX11: v_cmpx_class_f16_e32 v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7d]
-v_cmpx_class_f16 s1, v2
-// GFX11: v_cmpx_class_f16_e32 s1, v2 ; encoding: [0x01,0x04,0xfa,0x7d]
+v_cmpx_class_f16 s1, v2.l
+// GFX11: v_cmpx_class_f16_e32 s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7d]
-v_cmpx_class_f16 s105, v2
-// GFX11: v_cmpx_class_f16_e32 s105, v2 ; encoding: [0x69,0x04,0xfa,0x7d]
+v_cmpx_class_f16 s105, v2.l
+// GFX11: v_cmpx_class_f16_e32 s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7d]
-v_cmpx_class_f16 vcc_lo, v2
-// GFX11: v_cmpx_class_f16_e32 vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7d]
+v_cmpx_class_f16 vcc_lo, v2.l
+// GFX11: v_cmpx_class_f16_e32 vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7d]
-v_cmpx_class_f16 vcc_hi, v2
-// GFX11: v_cmpx_class_f16_e32 vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7d]
+v_cmpx_class_f16 vcc_hi, v2.l
+// GFX11: v_cmpx_class_f16_e32 vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7d]
-v_cmpx_class_f16 ttmp15, v2
-// GFX11: v_cmpx_class_f16_e32 ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7d]
+v_cmpx_class_f16 ttmp15, v2.l
+// GFX11: v_cmpx_class_f16_e32 ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7d]
-v_cmpx_class_f16 m0, v2
-// GFX11: v_cmpx_class_f16_e32 m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7d]
+v_cmpx_class_f16 m0, v2.l
+// GFX11: v_cmpx_class_f16_e32 m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7d]
-v_cmpx_class_f16 exec_lo, v2
-// GFX11: v_cmpx_class_f16_e32 exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7d]
+v_cmpx_class_f16 exec_lo, v2.l
+// GFX11: v_cmpx_class_f16_e32 exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7d]
-v_cmpx_class_f16 exec_hi, v2
-// GFX11: v_cmpx_class_f16_e32 exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7d]
+v_cmpx_class_f16 exec_hi, v2.l
+// GFX11: v_cmpx_class_f16_e32 exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7d]
-v_cmpx_class_f16 null, v2
-// GFX11: v_cmpx_class_f16_e32 null, v2 ; encoding: [0x7c,0x04,0xfa,0x7d]
+v_cmpx_class_f16 null, v2.l
+// GFX11: v_cmpx_class_f16_e32 null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7d]
-v_cmpx_class_f16 -1, v2
-// GFX11: v_cmpx_class_f16_e32 -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7d]
+v_cmpx_class_f16 -1, v2.l
+// GFX11: v_cmpx_class_f16_e32 -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7d]
-v_cmpx_class_f16 0.5, v2
-// GFX11: v_cmpx_class_f16_e32 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7d]
+v_cmpx_class_f16 0.5, v2.l
+// GFX11: v_cmpx_class_f16_e32 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7d]
-v_cmpx_class_f16 src_scc, v2
-// GFX11: v_cmpx_class_f16_e32 src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7d]
+v_cmpx_class_f16 src_scc, v2.l
+// GFX11: v_cmpx_class_f16_e32 src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7d]
-v_cmpx_class_f16 0xfe0b, v127
-// GFX11: v_cmpx_class_f16_e32 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+v_cmpx_class_f16 0xfe0b, v127.l
+// GFX11: v_cmpx_class_f16_e32 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f16 v1.h, v2.l
+// GFX11: v_cmpx_class_f16_e32 v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7d]
+
+v_cmpx_class_f16 v127.h, v2.l
+// GFX11: v_cmpx_class_f16_e32 v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7d]
+
+v_cmpx_class_f16 0.5, v127.l
+// GFX11: v_cmpx_class_f16_e32 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7d]
+
+v_cmpx_class_f16 src_scc, v2.h
+// GFX11: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
+
+v_cmpx_class_f16 0xfe0b, v127.h
+// GFX11: v_cmpx_class_f16_e32 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
v_cmpx_class_f32 v1, v2
// GFX11: v_cmpx_class_f32_e32 v1, v2 ; encoding: [0x01,0x05,0xfc,0x7d]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
index b2ea4348f33b89..5d58d8f18becc3 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
@@ -2,47 +2,56 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_cmpx_class_f16_dpp v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_cmpx_class_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16 v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_cmpx_class_f16 v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16 v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_cmpx_class_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff]
+v_cmpx_class_f16 v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_cmpx_class_f16 v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff]
-v_cmpx_class_f16 v1, v2 row_mirror
-// GFX11: v_cmpx_class_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_mirror
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_half_mirror
-// GFX11: v_cmpx_class_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_half_mirror
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shl:1
-// GFX11: v_cmpx_class_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shl:1
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shl:15
-// GFX11: v_cmpx_class_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shl:15
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shr:1
-// GFX11: v_cmpx_class_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shr:1
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shr:15
-// GFX11: v_cmpx_class_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shr:15
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_ror:1
-// GFX11: v_cmpx_class_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_ror:1
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_ror:15
-// GFX11: v_cmpx_class_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_ror:15
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: v_cmpx_class_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: v_cmpx_class_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01]
+v_cmpx_class_f16 v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01]
-v_cmpx_class_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: v_cmpx_class_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x60,0x09,0x13]
+v_cmpx_class_f16 v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// GFX11: v_cmpx_class_f16 v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x60,0x09,0x13]
-v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x35,0x30]
+v_cmpx_class_f16 -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// GFX11: v_cmpx_class_f16 -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x35,0x30]
+
+v_cmpx_class_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_cmpx_class_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x5f,0x01,0x01]
+
+v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x09,0x13]
+
+v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x35,0x30]
v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
index b4c556cf0328a9..84bdea6adb5bfb 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
@@ -2,14 +2,23 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_cmpx_class_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+v_cmpx_class_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// GFX11: v_cmpx_class_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_class_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
index ec628dd94f366b..7b42e03c6e1445 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
@@ -1,23 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
-v_cmpx_class_f16_e32 v1, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmpx_class_f16_e32 v1.h, v255.h
+// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v1, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v255, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmpx_class_f16_e32 v1.l, v255.l
+// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v255.h, v2.h
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v255, v2 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v255.l, v2.l
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
v_cmpx_eq_f16_e32 v1, v255
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
index 3bbdf3d3a903f8..9a6a1135c858a9 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
@@ -1,23 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
-v_cmpx_class_f16 v1, v255
-// GFX11: v_cmpx_class_f16_e64 v1, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xff,0x03,0x00]
+v_cmpx_class_f16 v1.h, v255.h
+// GFX11: v_cmpx_class_f16_e64 v1.h, v255.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0xff,0x03,0x00]
-v_cmpx_class_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v1, v255 quad_perm:[3,2,1,0]
-// GFX11: v_cmpx_class_f16_e64_dpp v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16 v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16 v255, v2
-// GFX11: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+v_cmpx_class_f16 v1.l, v255.l
+// GFX11: v_cmpx_class_f16_e64 v1.l, v255.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xff,0x03,0x00]
-v_cmpx_class_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmpx_class_f16_e64_dpp v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v255, v2 quad_perm:[3,2,1,0]
-// GFX11: v_cmpx_class_f16_e64_dpp v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+v_cmpx_class_f16 v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_class_f16 v255.h, v2.h
+// GFX11: v_cmpx_class_f16_e64 v255.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16 v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v255.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v255.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+
+v_cmpx_class_f16 v255.l, v2.l
+// GFX11: v_cmpx_class_f16_e64 v255.l, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16 v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_cmpx_class_f16_e64_dpp v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
v_cmpx_eq_f16 v1, v255
// GFX11: v_cmpx_eq_f16_e64 v1, v255 ; encoding: [0x7e,0x00,0x82,0xd4,0x01,0xff,0x03,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
index 476ea846f603a4..5589749d3d4f0f 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
@@ -2,17 +2,17 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
-v_cmpx_class_f16_e64 v1, v2
-// GFX12: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+v_cmpx_class_f16_e64 v1.l, v2.l
+// GFX12: v_cmpx_class_f16_e64 v1.l, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
-v_cmpx_class_f16_e64 v255, v2
-// GFX12: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+v_cmpx_class_f16_e64 v255.l, v2.l
+// GFX12: v_cmpx_class_f16_e64 v255.l, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
-v_cmpx_class_f16_e64 s1, v2
-// GFX12: v_cmpx_class_f16_e64 s1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+v_cmpx_class_f16_e64 s1, v2.l
+// GFX12: v_cmpx_class_f16_e64 s1, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
-v_cmpx_class_f16_e64 s105, v255
-// GFX12: v_cmpx_class_f16_e64 s105, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+v_cmpx_class_f16_e64 s105, v255.l
+// GFX12: v_cmpx_class_f16_e64 s105, v255.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
v_cmpx_class_f16_e64 vcc_lo, s2
// GFX12: v_cmpx_class_f16_e64 vcc_lo, s2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00]
@@ -47,6 +47,15 @@ v_cmpx_class_f16_e64 src_scc, vcc_lo
v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi
// GFX12: v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi ; encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+v_cmpx_class_f16_e64 v1.h, v2.h
+// GFX12: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 v255.h, v2.l
+// GFX12: v_cmpx_class_f16_e64 v255.h, v2.l op_sel:[1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s105, v255.h
+// GFX12: v_cmpx_class_f16_e64 s105, v255.h op_sel:[0,1] ; encoding: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+
v_cmpx_class_f32_e64 v1, v2
// GFX12: v_cmpx_class_f32_e64 v1, v2 ; encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
index a6953ecc1d78a0..313b119ceae7df 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
@@ -2,53 +2,62 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
-v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16_e64_dpp v1, s2 quad_perm:[3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, s2 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16_e64_dpp v1, 2.0 quad_perm:[3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, 2.0 quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_mirror
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_mirror
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_half_mirror
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_half_mirror
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shl:1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shl:15
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:15
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shr:1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_shr:15
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:15
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_ror:1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_ror:15
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:15
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_cmpx_class_f16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
-v_cmpx_class_f16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
-v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX12: v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.h row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.h, v2.h op_sel:[1,1] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7e,0x08,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
+
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7e,0x11,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0]
// GFX12: v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
index 8e2899086f2bd9..3a83cf840c39f4 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
@@ -2,20 +2,29 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
-v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16_e64_dpp v1, s2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, s2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16_e64_dpp v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16_e64_dpp v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX12: v_cmpx_class_f16_e64_dpp v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16_e64_dpp v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX12: v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7e,0x01,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7e,0x01,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16_e64_dpp v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x08,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7e,0x11,0xfd,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX12: v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
index 300c7481451419..7a638adb3c34a7 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
@@ -2,50 +2,62 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
-v_cmpx_class_f16_e32 v1, v2
-// GFX12: v_cmpx_class_f16_e32 v1, v2 ; encoding: [0x01,0x05,0xfa,0x7d]
+v_cmpx_class_f16 v1.l, v2.l
+// GFX12: v_cmpx_class_f16_e32 v1.l, v2.l ; encoding: [0x01,0x05,0xfa,0x7d]
-v_cmpx_class_f16 v127, v2
-// GFX12: v_cmpx_class_f16_e32 v127, v2 ; encoding: [0x7f,0x05,0xfa,0x7d]
+v_cmpx_class_f16 v127.l, v2.l
+// GFX12: v_cmpx_class_f16_e32 v127.l, v2.l ; encoding: [0x7f,0x05,0xfa,0x7d]
-v_cmpx_class_f16 s1, v2
-// GFX12: v_cmpx_class_f16_e32 s1, v2 ; encoding: [0x01,0x04,0xfa,0x7d]
+v_cmpx_class_f16 s1, v2.l
+// GFX12: v_cmpx_class_f16_e32 s1, v2.l ; encoding: [0x01,0x04,0xfa,0x7d]
-v_cmpx_class_f16 s105, v2
-// GFX12: v_cmpx_class_f16_e32 s105, v2 ; encoding: [0x69,0x04,0xfa,0x7d]
+v_cmpx_class_f16 s105, v2.l
+// GFX12: v_cmpx_class_f16_e32 s105, v2.l ; encoding: [0x69,0x04,0xfa,0x7d]
-v_cmpx_class_f16 vcc_lo, v2
-// GFX12: v_cmpx_class_f16_e32 vcc_lo, v2 ; encoding: [0x6a,0x04,0xfa,0x7d]
+v_cmpx_class_f16 vcc_lo, v2.l
+// GFX12: v_cmpx_class_f16_e32 vcc_lo, v2.l ; encoding: [0x6a,0x04,0xfa,0x7d]
-v_cmpx_class_f16 vcc_hi, v2
-// GFX12: v_cmpx_class_f16_e32 vcc_hi, v2 ; encoding: [0x6b,0x04,0xfa,0x7d]
+v_cmpx_class_f16 vcc_hi, v2.l
+// GFX12: v_cmpx_class_f16_e32 vcc_hi, v2.l ; encoding: [0x6b,0x04,0xfa,0x7d]
-v_cmpx_class_f16 ttmp15, v2
-// GFX12: v_cmpx_class_f16_e32 ttmp15, v2 ; encoding: [0x7b,0x04,0xfa,0x7d]
+v_cmpx_class_f16 ttmp15, v2.l
+// GFX12: v_cmpx_class_f16_e32 ttmp15, v2.l ; encoding: [0x7b,0x04,0xfa,0x7d]
-v_cmpx_class_f16 m0, v2
-// GFX12: v_cmpx_class_f16_e32 m0, v2 ; encoding: [0x7d,0x04,0xfa,0x7d]
+v_cmpx_class_f16 m0, v2.l
+// GFX12: v_cmpx_class_f16_e32 m0, v2.l ; encoding: [0x7d,0x04,0xfa,0x7d]
-v_cmpx_class_f16 exec_lo, v2
-// GFX12: v_cmpx_class_f16_e32 exec_lo, v2 ; encoding: [0x7e,0x04,0xfa,0x7d]
+v_cmpx_class_f16 exec_lo, v2.l
+// GFX12: v_cmpx_class_f16_e32 exec_lo, v2.l ; encoding: [0x7e,0x04,0xfa,0x7d]
-v_cmpx_class_f16 exec_hi, v2
-// GFX12: v_cmpx_class_f16_e32 exec_hi, v2 ; encoding: [0x7f,0x04,0xfa,0x7d]
+v_cmpx_class_f16 exec_hi, v2.l
+// GFX12: v_cmpx_class_f16_e32 exec_hi, v2.l ; encoding: [0x7f,0x04,0xfa,0x7d]
-v_cmpx_class_f16 null, v2
-// GFX12: v_cmpx_class_f16_e32 null, v2 ; encoding: [0x7c,0x04,0xfa,0x7d]
+v_cmpx_class_f16 null, v2.l
+// GFX12: v_cmpx_class_f16_e32 null, v2.l ; encoding: [0x7c,0x04,0xfa,0x7d]
-v_cmpx_class_f16 -1, v2
-// GFX12: v_cmpx_class_f16_e32 -1, v2 ; encoding: [0xc1,0x04,0xfa,0x7d]
+v_cmpx_class_f16 -1, v2.l
+// GFX12: v_cmpx_class_f16_e32 -1, v2.l ; encoding: [0xc1,0x04,0xfa,0x7d]
-v_cmpx_class_f16 0.5, v2
-// GFX12: v_cmpx_class_f16_e32 0.5, v2 ; encoding: [0xf0,0x04,0xfa,0x7d]
+v_cmpx_class_f16 0.5, v2.l
+// GFX12: v_cmpx_class_f16_e32 0.5, v2.l ; encoding: [0xf0,0x04,0xfa,0x7d]
-v_cmpx_class_f16 src_scc, v2
-// GFX12: v_cmpx_class_f16_e32 src_scc, v2 ; encoding: [0xfd,0x04,0xfa,0x7d]
+v_cmpx_class_f16 src_scc, v2.l
+// GFX12: v_cmpx_class_f16_e32 src_scc, v2.l ; encoding: [0xfd,0x04,0xfa,0x7d]
-v_cmpx_class_f16 0xfe0b, v127
-// GFX12: v_cmpx_class_f16_e32 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+v_cmpx_class_f16 0xfe0b, v127.l
+// GFX12: v_cmpx_class_f16_e32 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f16 v1.h, v2.l
+// GFX12: v_cmpx_class_f16_e32 v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7d]
+
+v_cmpx_class_f16 v127.h, v2.l
+// GFX12: v_cmpx_class_f16_e32 v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7d]
+
+v_cmpx_class_f16 src_scc, v2.h
+// GFX12: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
+
+v_cmpx_class_f16 0xfe0b, v127.h
+// GFX12: v_cmpx_class_f16_e32 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
v_cmpx_class_f32 v1, v2
// GFX12: v_cmpx_class_f32_e32 v1, v2 ; encoding: [0x01,0x05,0xfc,0x7d]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
index 857d6267a215fe..4963f31e7918b0 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
@@ -2,47 +2,53 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
-v_cmpx_class_f16_dpp v1, v2 quad_perm:[3,2,1,0]
-// GFX12: v_cmpx_class_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16 v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16 v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16 v1, v2 quad_perm:[0,1,2,3]
-// GFX12: v_cmpx_class_f16 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff]
+v_cmpx_class_f16 v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX12: v_cmpx_class_f16 v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0xe4,0x00,0xff]
-v_cmpx_class_f16 v1, v2 row_mirror
-// GFX12: v_cmpx_class_f16 v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_mirror
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x40,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_half_mirror
-// GFX12: v_cmpx_class_f16 v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_half_mirror
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x41,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shl:1
-// GFX12: v_cmpx_class_f16 v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shl:1
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x01,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shl:15
-// GFX12: v_cmpx_class_f16 v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shl:15
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x0f,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shr:1
-// GFX12: v_cmpx_class_f16 v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shr:1
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x11,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_shr:15
-// GFX12: v_cmpx_class_f16 v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_shr:15
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1f,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_ror:1
-// GFX12: v_cmpx_class_f16 v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_ror:1
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x21,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_ror:15
-// GFX12: v_cmpx_class_f16 v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_ror:15
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x2f,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX12: v_cmpx_class_f16 v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff]
+v_cmpx_class_f16 v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x50,0x01,0xff]
-v_cmpx_class_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX12: v_cmpx_class_f16 v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01]
+v_cmpx_class_f16 v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x5f,0x01,0x01]
-v_cmpx_class_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX12: v_cmpx_class_f16 v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x60,0x09,0x13]
+v_cmpx_class_f16 v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// GFX12: v_cmpx_class_f16 v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x60,0x09,0x13]
-v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX12: v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x35,0x30]
+v_cmpx_class_f16 -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// GFX12: v_cmpx_class_f16 -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x35,0x30]
+
+v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x09,0x13]
+
+v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x35,0x30]
v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0]
// GFX12: v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
index 8ee6b7d488fdfd..367b56687fe469 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
@@ -2,14 +2,20 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
-v_cmpx_class_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX12: v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX12: v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+v_cmpx_class_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: v_cmpx_class_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+
+v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX12: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
index 5019324d174b87..5f3353d9a3034c 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
@@ -1,23 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s
-v_cmpx_class_f16_e32 v1, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmpx_class_f16_e32 v1.h, v255.h
+// GFX12: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v1, v255 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:28: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v255, v2
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmpx_class_f16_e32 v1.l, v255.l
+// GFX12: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:28: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.h, v2.h
+// GFX12: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:22: error: invalid operand for instruction
+
+v_cmpx_class_f16_e32 v255.l, v2.l
+// GFX12: :[[@LINE-1]]:22: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:22: error: invalid operand for instruction
-v_cmpx_class_f16_e32 v255, v2 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+v_cmpx_class_f16_e32 v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:22: error: invalid operand for instruction
v_cmpx_eq_f16_e32 v1, v255
// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
index 4f462861e3a0b0..82e58f16d00044 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
@@ -1,23 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 %s
-v_cmpx_class_f16 v1, v255
-// GFX12: v_cmpx_class_f16_e64 v1, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xff,0x03,0x00]
+v_cmpx_class_f16 v1.h, v255.h
+// GFX12: v_cmpx_class_f16_e64 v1.h, v255.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0xff,0x03,0x00]
-v_cmpx_class_f16 v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v1, v255 quad_perm:[3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_cmpx_class_f16 v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_cmpx_class_f16 v255, v2
-// GFX12: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+v_cmpx_class_f16 v1.l, v255.l
+// GFX12: v_cmpx_class_f16_e64 v1.l, v255.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0xff,0x03,0x00]
-v_cmpx_class_f16 v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+v_cmpx_class_f16 v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmpx_class_f16 v255, v2 quad_perm:[3,2,1,0]
-// GFX12: v_cmpx_class_f16_e64_dpp v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+v_cmpx_class_f16 v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+
+v_cmpx_class_f16 v255.h, v2.h
+// GFX12: v_cmpx_class_f16_e64 v255.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16 v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v255.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v255.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+
+v_cmpx_class_f16 v255.l, v2.l
+// GFX12: v_cmpx_class_f16_e64 v255.l, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16 v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_cmpx_class_f16 v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_cmpx_class_f16_e64_dpp v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
v_cmpx_eq_f16 v1, v255
// GFX12: v_cmpx_eq_f16_e64 v1, v255 ; encoding: [0x7e,0x00,0x82,0xd4,0x01,0xff,0x03,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
index 4ce26199bcc081..80cdb3ebae2f09 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
@@ -46,6 +46,15 @@
0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
# GFX11: v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.h op_sel:[1,1] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x08,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x08,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX11: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x11,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7e,0x11,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
+
0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
# GFX11: v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
index a703568f5c6f21..837f9471125373 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
@@ -10,6 +10,15 @@
0x7e,0x01,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
# GFX11: v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x08,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX11: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x11,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+0x7e,0x11,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
+
0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
# GFX11: v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
index d519c0ffa66c65..3fcdaec457c773 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
@@ -52,6 +52,15 @@
0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00
# GFX11: v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi ; encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+# GFX11: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00
+
+# GFX11: v_cmpx_class_f16_e64 v255.h, v2.l op_sel:[1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00
+
+# GFX11: v_cmpx_class_f16_e64 s105, v255.h op_sel:[0,1] ; encoding: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00
+
0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00
# GFX11: v_cmpx_class_f32_e64 v1, v2 ; encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
index e0b5c16c27d2f4..79c258d401f803 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
@@ -49,6 +49,36 @@
0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00
# GFX11: v_cmpx_class_f16_e32 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+0x81,0x05,0xfa,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7d]
+
+0xff,0x05,0xfa,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7d]
+
+0xf0,0xfe,0xfa,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 0.5, v127 ; encoding: [0xf0,0xfe,0xfa,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 0.5, v127.l ; encoding: [0xf0,0xfe,0xfa,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 0.5, v127 ; encoding: [0xf0,0xfe,0xfa,0x7d]
+
+0xfd,0x04,0xfb,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7d]
+
+0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00
+# W32-REAL16: v_cmpx_class_f16_e32 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e32 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+# W64-REAL16: v_cmpx_class_f16_e32 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e32 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+
0x01,0x05,0xfc,0x7d
# GFX11: v_cmpx_class_f32_e32 v1, v2 ; encoding: [0x01,0x05,0xfc,0x7d]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
index 1d7e82c8bf96f2..572db5e8e3d16f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
@@ -46,6 +46,24 @@
0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x3d,0x30
# GFX11: v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x3d,0x30]
+0xfa,0xfe,0xfa,0x7d,0x7f,0x5f,0x01,0x01
+# W32-REAL16: v_cmpx_class_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x5f,0x01,0x01]
+# W32-FAKE16: v_cmpx_class_f16 v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x5f,0x01,0x01]
+# W64-REAL16: v_cmpx_class_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x5f,0x01,0x01]
+# W64-FAKE16: v_cmpx_class_f16 v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x5f,0x01,0x01]
+
+0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13
+# W32-REAL16: v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+# W32-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+# W64-REAL16: v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+# W64-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+
+0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30
+# W32-REAL16: v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+# W32-FAKE16: v_cmpx_class_f16 -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+# W64-REAL16: v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+# W64-FAKE16: v_cmpx_class_f16 -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+
0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff
# GFX11: v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
index a6d8ec95d6d632..a4d27fc3b6e7b1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
@@ -10,6 +10,24 @@
0xea,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00
# GFX11: v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+0xe9,0xfe,0xfa,0x7d,0x7f,0x77,0x39,0x05
+# W32-REAL16: v_cmpx_class_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x77,0x39,0x05]
+# W32-FAKE16: v_cmpx_class_f16 v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x77,0x39,0x05]
+# W64-REAL16: v_cmpx_class_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x77,0x39,0x05]
+# W64-FAKE16: v_cmpx_class_f16 v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfa,0x7d,0x7f,0x77,0x39,0x05]
+
+0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05
+# W32-REAL16: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+# W32-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+# W64-REAL16: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+# W64-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+
+0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00
+# W32-REAL16: v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmpx_class_f16 v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmpx_class_f16 v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+
0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05
# GFX11: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
index 46f255c2f484f3..a6ac8336909a6c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
@@ -49,6 +49,26 @@
0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00
# GFX12: v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi ; encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
+0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 v255.h, v2.l op_sel:[1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 v255.h, v2.l op_sel:[1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 s105, v255.h op_sel:[0,1] ; encoding: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 s105, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 s105, v255.h op_sel:[0,1] ; encoding: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 s105, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+
+# GFX11: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00
# GFX12: v_cmpx_class_f32_e64 v1, v2 ; encoding: [0x7e,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
index 3550b6fc5e95df..a253e0b29589da 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
@@ -49,6 +49,72 @@
0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
# GFX12: v_cmpx_class_f16_e64_dpp -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 v1.h, v2.h op_sel:[1,1] ; encoding: [0x7e,0x18,0xfd,0xd4,0x01,0x05,0x02,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
+0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 v255.h, v2.l op_sel:[1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 v255.h, v2.l op_sel:[1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xff,0x05,0x02,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 v255, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 s1, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 s1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 s1, v2.l ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 s1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+
+0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00
+# W32-REAL16: v_cmpx_class_f16_e64 s105, v255.h op_sel:[0,1] ; encoding: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e64 s105, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+# W64-REAL16: v_cmpx_class_f16_e64 s105, v255.h op_sel:[0,1] ; encoding: [0x7e,0x10,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e64 s105, v255 ; encoding: [0x7e,0x00,0xfd,0xd4,0x69,0xfe,0x03,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 vcc_lo, s2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x6a,0x04,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x6b,0xd2,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 vcc_hi, s105 ; encoding: [0x7e,0x00,0xfd,0xd4,0x6b,0xd2,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x7b,0xf6,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 ttmp15, ttmp15 ; encoding: [0x7e,0x00,0xfd,0xd4,0x7b,0xf6,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00
+# GFX12: v_cmpx_class_f16_e64 m0, src_scc ; encoding: [0x7e,0x00,0xfd,0xd4,0x7d,0xfa,0x01,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x7e,0x82,0x01,0x00
+# GFX12: v_cmpx_class_f16_e64 exec_lo, -1 ; encoding: [0x7e,0x00,0xfd,0xd4,0x7e,0x82,0x01,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x7f,0xf8,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 exec_hi, null ; encoding: [0x7e,0x00,0xfd,0xd4,0x7f,0xf8,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0x7c,0xfc,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 null, exec_lo ; encoding: [0x7e,0x00,0xfd,0xd4,0x7c,0xfc,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0xc1,0xfe,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 -1, exec_hi ; encoding: [0x7e,0x00,0xfd,0xd4,0xc1,0xfe,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0xf0,0xfa,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 0.5, m0 ; encoding: [0x7e,0x00,0xfd,0xd4,0xf0,0xfa,0x00,0x00]
+
+0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 src_scc, vcc_lo ; encoding: [0x7e,0x00,0xfd,0xd4,0xfd,0xd4,0x00,0x00]
+
+0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00
+# GFX12: v_cmpx_class_f16_e64 -|0xfe0b|, vcc_hi ; encoding: [0x7e,0x01,0xfd,0xd4,0xff,0xd6,0x00,0x20,0x0b,0xfe,0x00,0x00]
+
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.h op_sel:[1,1] row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
+0x7e,0x18,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01
+
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7e,0x08,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
+0x7e,0x08,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13
+
+# GFX11: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h op_sel:[0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7e,0x11,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
+0x7e,0x11,0xfd,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30
+
0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
index 9442dcc4fb1d55..ba9db83a5e9077 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
@@ -13,6 +13,15 @@
0x7e,0x01,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
# GFX12: v_cmpx_class_f16_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x01,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x18,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x08,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+0x7e,0x08,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
+
+# GFX11: v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h op_sel:[0,1] dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7e,0x11,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
+0x7e,0x11,0xfd,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00
+
0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
# GFX12: v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfe,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
index 180ec987280d18..9d8ab3b4f4db01 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
@@ -49,6 +49,30 @@
0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00
# GFX12: v_cmpx_class_f16_e32 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+0x81,0x05,0xfa,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 v1.h, v2.l ; encoding: [0x81,0x05,0xfa,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0xfa,0x7d]
+
+0xff,0x05,0xfa,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 v127.h, v2.l ; encoding: [0xff,0x05,0xfa,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0xfa,0x7d]
+
+0xfd,0x04,0xfb,0x7d
+# W32-REAL16: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
+# W32-FAKE16: v_cmpx_class_f16_e32 src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7d]
+# W64-REAL16: v_cmpx_class_f16_e32 src_scc, v2.h ; encoding: [0xfd,0x04,0xfb,0x7d]
+# W64-FAKE16: v_cmpx_class_f16_e32 src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0xfb,0x7d]
+
+0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00
+# W32-REAL16: v_cmpx_class_f16_e32 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+# W32-FAKE16: v_cmpx_class_f16_e32 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+# W64-REAL16: v_cmpx_class_f16_e32 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+# W64-FAKE16: v_cmpx_class_f16_e32 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0xfb,0x7d,0x0b,0xfe,0x00,0x00]
+
0x01,0x05,0xfc,0x7d
# GFX12: v_cmpx_class_f32_e32 v1, v2 ; encoding: [0x01,0x05,0xfc,0x7d]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
index e65d451116d292..61a3b3b851b004 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
@@ -46,6 +46,18 @@
0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x3d,0x30
# GFX12: v_cmpx_class_f16 -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfa,0x7d,0x7f,0x6f,0x3d,0x30]
+0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13
+# W32-REAL16: v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+# W32-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+# W64-REAL16: v_cmpx_class_f16 v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+# W64-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0xfb,0x7d,0x81,0x60,0x01,0x13]
+
+0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30
+# W32-REAL16: v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+# W32-FAKE16: v_cmpx_class_f16 -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+# W64-REAL16: v_cmpx_class_f16 -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+# W64-FAKE16: v_cmpx_class_f16 -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfb,0x7d,0xff,0x6f,0x3d,0x30]
+
0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff
# GFX12: v_cmpx_class_f32 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfc,0x7d,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
index 4449cbcfb36080..b4945f9e14564c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
@@ -10,6 +10,18 @@
0xea,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00
# GFX12: v_cmpx_class_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7d,0x7f,0x00,0x00,0x00]
+0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05
+# W32-REAL16: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+# W32-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+# W64-REAL16: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+# W64-FAKE16: v_cmpx_class_f16 v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
+
+0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00
+# W32-REAL16: v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmpx_class_f16 v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmpx_class_f16 v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7d,0xff,0x00,0x00,0x00]
+
0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05
# GFX12: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
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