[llvm] ff1b01b - [llvm-exegesis] Begin replacing unsigned with MCRegister. NFC (#123109)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 16 08:23:49 PST 2025
Author: Craig Topper
Date: 2025-01-16T08:23:46-08:00
New Revision: ff1b01bb7897bf2401540096af775d35b12eb247
URL: https://github.com/llvm/llvm-project/commit/ff1b01bb7897bf2401540096af775d35b12eb247
DIFF: https://github.com/llvm/llvm-project/commit/ff1b01bb7897bf2401540096af775d35b12eb247.diff
LOG: [llvm-exegesis] Begin replacing unsigned with MCRegister. NFC (#123109)
Some of this was needed to fix implicit conversions from MCRegister to
unsigned when calling getReg() on MCOperand for example.
The majority was done by reviewing parts of the code that dealt with
registers, converting them to MCRegister and then seeing what new
implicit conversions were created and fixing those.
There were a few places where I used MCPhysReg instead of MCRegiser for
static arrays since its uint16_t instead of unsigned.
Added:
Modified:
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
llvm/tools/llvm-exegesis/lib/Assembler.cpp
llvm/tools/llvm-exegesis/lib/Assembler.h
llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
llvm/tools/llvm-exegesis/lib/CodeTemplate.h
llvm/tools/llvm-exegesis/lib/LlvmState.cpp
llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.cpp
llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.h
llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
llvm/tools/llvm-exegesis/lib/RegisterAliasing.h
llvm/tools/llvm-exegesis/lib/RegisterValue.h
llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
llvm/tools/llvm-exegesis/lib/SnippetRepetitor.h
llvm/tools/llvm-exegesis/lib/Target.cpp
llvm/tools/llvm-exegesis/lib/Target.h
llvm/tools/llvm-exegesis/lib/X86/Target.cpp
llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Removed:
################################################################################
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 51846862f0a734..5a7cc6f5e30d38 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -26,7 +26,7 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
}
// Generates instruction to load an immediate value into a register.
-static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
+static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
const APInt &Value) {
if (Value.getBitWidth() > RegBitWidth)
llvm_unreachable("Value must fit in the Register");
@@ -45,7 +45,7 @@ class ExegesisAArch64Target : public ExegesisTarget {
: ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
private:
- std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override {
if (AArch64::GPR32RegClass.contains(Reg))
return {loadImmediate(Reg, 32, Value)};
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 13c8c2048a5c03..7a53b626c177c0 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -81,7 +81,7 @@ static bool generateSnippetSetupCode(const ExegesisTarget &ET,
// If we're generating memory instructions, don't load in the value for
// the register with the stack pointer as it will be used later to finish
// the setup.
- if (RV.Register == StackPointerRegister)
+ if (Register(RV.Register) == StackPointerRegister)
continue;
}
// Load a constant in the register.
@@ -98,7 +98,7 @@ static bool generateSnippetSetupCode(const ExegesisTarget &ET,
// Load in the stack register now as we're done using it elsewhere
// and need to set the value in preparation for executing the
// snippet.
- if (RV.Register != StackPointerRegister)
+ if (Register(RV.Register) != StackPointerRegister)
continue;
const auto SetRegisterCode = ET.setRegTo(*MSI, RV.Register, RV.Value);
if (SetRegisterCode.empty())
@@ -208,7 +208,7 @@ void BasicBlockFiller::addReturn(const ExegesisTarget &ET,
}
FunctionFiller::FunctionFiller(MachineFunction &MF,
- std::vector<unsigned> RegistersSetUp)
+ std::vector<MCRegister> RegistersSetUp)
: MF(MF), MCII(MF.getTarget().getMCInstrInfo()), Entry(addBasicBlock()),
RegistersSetUp(std::move(RegistersSetUp)) {}
@@ -218,7 +218,7 @@ BasicBlockFiller FunctionFiller::addBasicBlock() {
return BasicBlockFiller(MF, MBB, MCII);
}
-ArrayRef<unsigned> FunctionFiller::getRegistersSetUp() const {
+ArrayRef<MCRegister> FunctionFiller::getRegistersSetUp() const {
return RegistersSetUp;
}
@@ -241,7 +241,7 @@ BitVector getFunctionReservedRegs(const TargetMachine &TM) {
Error assembleToStream(const ExegesisTarget &ET,
std::unique_ptr<TargetMachine> TM,
- ArrayRef<unsigned> LiveIns, const FillFunction &Fill,
+ ArrayRef<MCRegister> LiveIns, const FillFunction &Fill,
raw_pwrite_stream &AsmStream, const BenchmarkKey &Key,
bool GenerateMemoryInstructions) {
auto Context = std::make_unique<LLVMContext>();
@@ -259,19 +259,19 @@ Error assembleToStream(const ExegesisTarget &ET,
Properties.reset(MachineFunctionProperties::Property::IsSSA);
Properties.set(MachineFunctionProperties::Property::NoPHIs);
- for (const unsigned Reg : LiveIns)
+ for (const MCRegister Reg : LiveIns)
MF.getRegInfo().addLiveIn(Reg);
if (GenerateMemoryInstructions) {
- for (const unsigned Reg : ET.getArgumentRegisters())
+ for (const MCRegister Reg : ET.getArgumentRegisters())
MF.getRegInfo().addLiveIn(Reg);
// Add a live in for registers that need saving so that the machine verifier
// doesn't fail if the register is never defined.
- for (const unsigned Reg : ET.getRegistersNeedSaving())
+ for (const MCRegister Reg : ET.getRegistersNeedSaving())
MF.getRegInfo().addLiveIn(Reg);
}
- std::vector<unsigned> RegistersSetUp;
+ std::vector<MCRegister> RegistersSetUp;
RegistersSetUp.reserve(Key.RegisterInitialValues.size());
for (const auto &InitValue : Key.RegisterInitialValues) {
RegistersSetUp.push_back(InitValue.Register);
@@ -279,15 +279,15 @@ Error assembleToStream(const ExegesisTarget &ET,
FunctionFiller Sink(MF, std::move(RegistersSetUp));
auto Entry = Sink.getEntry();
- for (const unsigned Reg : LiveIns)
+ for (const MCRegister Reg : LiveIns)
Entry.MBB->addLiveIn(Reg);
if (GenerateMemoryInstructions) {
- for (const unsigned Reg : ET.getArgumentRegisters())
+ for (const MCRegister Reg : ET.getArgumentRegisters())
Entry.MBB->addLiveIn(Reg);
// Add a live in for registers that need saving so that the machine verifier
// doesn't fail if the register is never defined.
- for (const unsigned Reg : ET.getRegistersNeedSaving())
+ for (const MCRegister Reg : ET.getRegistersNeedSaving())
Entry.MBB->addLiveIn(Reg);
}
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.h b/llvm/tools/llvm-exegesis/lib/Assembler.h
index 4d241e0281b5a7..1c8854c21b9a75 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.h
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.h
@@ -61,7 +61,7 @@ class BasicBlockFiller {
// Helper to fill in a function.
class FunctionFiller {
public:
- FunctionFiller(MachineFunction &MF, std::vector<unsigned> RegistersSetUp);
+ FunctionFiller(MachineFunction &MF, std::vector<MCRegister> RegistersSetUp);
// Adds a basic block to the function.
BasicBlockFiller addBasicBlock();
@@ -73,12 +73,12 @@ class FunctionFiller {
const MCInstrInfo *const MCII;
// Returns the set of registers in the snippet setup code.
- ArrayRef<unsigned> getRegistersSetUp() const;
+ ArrayRef<MCRegister> getRegistersSetUp() const;
private:
BasicBlockFiller Entry;
// The set of registers that are set up in the basic block.
- std::vector<unsigned> RegistersSetUp;
+ std::vector<MCRegister> RegistersSetUp;
};
// A callback that fills a function.
@@ -90,7 +90,7 @@ using FillFunction = std::function<void(FunctionFiller &)>;
// AsmStream, the temporary function is eventually discarded.
Error assembleToStream(const ExegesisTarget &ET,
std::unique_ptr<TargetMachine> TM,
- ArrayRef<unsigned> LiveIns, const FillFunction &Fill,
+ ArrayRef<MCRegister> LiveIns, const FillFunction &Fill,
raw_pwrite_stream &AsmStreamm, const BenchmarkKey &Key,
bool GenerateMemoryInstructions);
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h b/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
index 1db8472e99f7c9..5e3c10decf7236 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
@@ -23,7 +23,7 @@ struct BenchmarkCode {
// We also need to provide the registers that are live on entry for the
// assembler to generate proper prologue/epilogue.
- std::vector<unsigned> LiveIns;
+ std::vector<MCRegister> LiveIns;
// Informations about how this configuration was built.
std::string Info;
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
index 84dc23b343c6c0..1823a534a301aa 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
@@ -65,17 +65,17 @@ struct YamlContext {
raw_string_ostream &getErrorStream() { return ErrorStream; }
- StringRef getRegName(unsigned RegNo) {
- // Special case: RegNo 0 is NoRegister. We have to deal with it explicitly.
- if (RegNo == 0)
+ StringRef getRegName(MCRegister Reg) {
+ // Special case: Reg may be invalid. We have to deal with it explicitly.
+ if (!Reg.isValid())
return kNoRegister;
- const StringRef RegName = State->getRegInfo().getName(RegNo);
+ const StringRef RegName = State->getRegInfo().getName(Reg);
if (RegName.empty())
- ErrorStream << "No register with enum value '" << RegNo << "'\n";
+ ErrorStream << "No register with enum value '" << Reg.id() << "'\n";
return RegName;
}
- std::optional<unsigned> getRegNo(StringRef RegName) {
+ std::optional<MCRegister> getRegNo(StringRef RegName) {
std::optional<MCRegister> RegisterNumber =
State->getRegisterNumberFromName(RegName);
if (!RegisterNumber.has_value())
@@ -261,7 +261,7 @@ template <> struct ScalarTraits<exegesis::RegisterValue> {
String.split(Pieces, "=0x", /* MaxSplit */ -1,
/* KeepEmpty */ false);
YamlContext &Context = getTypedContext(Ctx);
- std::optional<unsigned> RegNo;
+ std::optional<MCRegister> RegNo;
if (Pieces.size() == 2 && (RegNo = Context.getRegNo(Pieces[0]))) {
RV.Register = *RegNo;
const unsigned BitsNeeded = APInt::getBitsNeeded(Pieces[1], kRadix);
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
index 3c09a8380146e5..7984c8805cadc1 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
@@ -75,7 +75,7 @@ struct BenchmarkKey {
// being used supports it.
uintptr_t SnippetAddress = 0;
// The register that should be used to hold the loop counter.
- unsigned LoopRegister;
+ MCRegister LoopRegister;
};
struct BenchmarkMeasure {
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
index 7aca224302a1ff..a65015b45b7864 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
@@ -131,7 +131,7 @@ struct CodeTemplate {
std::vector<InstructionTemplate> Instructions;
// If the template uses the provided scratch memory, the register in which
// the pointer to this memory is passed in to the function.
- unsigned ScratchSpacePointerInReg = 0;
+ MCRegister ScratchSpacePointerInReg;
#if defined(__GNUC__) && (defined(__clang__) || LLVM_GNUC_PREREQ(8, 0, 0))
// FIXME: GCC7 bug workaround. Drop #if after GCC7 no longer supported.
diff --git a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
index 4c44c59286ccfb..00d0d2cfd1cd36 100644
--- a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
+++ b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
@@ -83,7 +83,7 @@ LLVMState::LLVMState(std::unique_ptr<const TargetMachine> TM,
OpcodeNameToOpcodeIdxMapping(createOpcodeNameToOpcodeIdxMapping()),
RegNameToRegNoMapping(createRegNameToRegNoMapping()) {
BitVector ReservedRegs = getFunctionReservedRegs(getTargetMachine());
- for (const unsigned Reg : TheExegesisTarget->getUnavailableRegisters())
+ for (const MCPhysReg Reg : TheExegesisTarget->getUnavailableRegisters())
ReservedRegs.set(Reg);
RATC.reset(
new RegisterAliasingTrackerCache(getRegInfo(), std::move(ReservedRegs)));
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index c9225e51213e59..c002f68b427f78 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -38,7 +38,7 @@ bool Operand::isExplicit() const { return Info; }
bool Operand::isImplicit() const { return !Info; }
-bool Operand::isImplicitReg() const { return ImplicitReg; }
+bool Operand::isImplicitReg() const { return ImplicitReg.isValid(); }
bool Operand::isDef() const { return IsDef; }
@@ -64,7 +64,7 @@ unsigned Operand::getTiedToIndex() const { return *TiedToIndex; }
unsigned Operand::getVariableIndex() const { return *VariableIndex; }
-unsigned Operand::getImplicitReg() const {
+MCRegister Operand::getImplicitReg() const {
assert(ImplicitReg);
return ImplicitReg;
}
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
index d7712e21c32c1c..c1af10fa460a33 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
@@ -75,7 +75,7 @@ struct Operand {
unsigned getIndex() const;
unsigned getTiedToIndex() const;
unsigned getVariableIndex() const;
- unsigned getImplicitReg() const;
+ MCRegister getImplicitReg() const;
const RegisterAliasingTracker &getRegisterAliasing() const;
const MCOperandInfo &getExplicitOperandInfo() const;
@@ -85,7 +85,7 @@ struct Operand {
const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
const MCOperandInfo *Info = nullptr; // Set for Explicit Op.
std::optional<uint8_t> TiedToIndex; // Set for Reg&Explicit Op.
- MCPhysReg ImplicitReg = 0; // Non-0 for Implicit Op.
+ MCRegister ImplicitReg; // Non-0 for Implicit Op.
std::optional<uint8_t> VariableIndex; // Set for Explicit Op.
};
diff --git a/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp b/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
index 731e037c240df0..f9666d98e1e818 100644
--- a/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
@@ -58,12 +58,12 @@ class ExegesisMipsTarget : public ExegesisTarget {
: ExegesisTarget(MipsCpuPfmCounters, Mips_MC::isOpcodeAvailable) {}
private:
- unsigned getScratchMemoryRegister(const Triple &TT) const override;
+ MCRegister getScratchMemoryRegister(const Triple &TT) const override;
unsigned getMaxMemoryAccessSize() const override { return 64; }
- void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+ void fillMemoryOperands(InstructionTemplate &IT, MCRegister Reg,
unsigned Offset) const override;
- std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override;
bool matchesArch(Triple::ArchType Arch) const override {
return Arch == Triple::mips || Arch == Triple::mipsel ||
@@ -73,7 +73,7 @@ class ExegesisMipsTarget : public ExegesisTarget {
} // end anonymous namespace
// Generates instructions to load an immediate value into a register.
-static std::vector<MCInst> loadImmediate(unsigned Reg, bool IsGPR32,
+static std::vector<MCInst> loadImmediate(MCRegister Reg, bool IsGPR32,
const APInt &Value) {
unsigned ZeroReg;
unsigned ORi, LUi, SLL;
@@ -134,12 +134,13 @@ static std::vector<MCInst> loadImmediate(unsigned Reg, bool IsGPR32,
llvm_unreachable("Not implemented for values wider than 32 bits");
}
-unsigned ExegesisMipsTarget::getScratchMemoryRegister(const Triple &TT) const {
+MCRegister
+ExegesisMipsTarget::getScratchMemoryRegister(const Triple &TT) const {
return TT.isArch64Bit() ? Mips::A0_64 : Mips::A0;
}
void ExegesisMipsTarget::fillMemoryOperands(InstructionTemplate &IT,
- unsigned Reg,
+ MCRegister Reg,
unsigned Offset) const {
assert(!isInvalidMemoryInstr(IT.getInstr()) &&
"fillMemoryOperands requires a valid memory instruction");
@@ -149,7 +150,7 @@ void ExegesisMipsTarget::fillMemoryOperands(InstructionTemplate &IT,
}
std::vector<MCInst> ExegesisMipsTarget::setRegTo(const MCSubtargetInfo &STI,
- unsigned Reg,
+ MCRegister Reg,
const APInt &Value) const {
if (Mips::GPR32RegClass.contains(Reg))
return loadImmediate(Reg, true, Value);
diff --git a/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.cpp
index 114e274845e532..03506a2dd757c9 100644
--- a/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.cpp
@@ -90,9 +90,9 @@ static bool hasVariablesWithTiedOperands(const Instruction &Instr) {
ParallelSnippetGenerator::~ParallelSnippetGenerator() = default;
void ParallelSnippetGenerator::instantiateMemoryOperands(
- const unsigned ScratchSpacePointerInReg,
+ const MCRegister ScratchSpacePointerInReg,
std::vector<InstructionTemplate> &Instructions) const {
- if (ScratchSpacePointerInReg == 0)
+ if (!ScratchSpacePointerInReg)
return; // no memory operands.
const auto &ET = State.getExegesisTarget();
const unsigned MemStep = ET.getMaxMemoryAccessSize();
@@ -261,10 +261,10 @@ generateSnippetForInstrAvoidingDefUseOverlap(
if (Op.isReg() && Op.isImplicit() && !Op.isMemory()) {
assert(Op.isImplicitReg() && "Not an implicit register operand?");
if (Op.isUse())
- ImplicitUses.set(Op.getImplicitReg());
+ ImplicitUses.set(Op.getImplicitReg().id());
else {
assert(Op.isDef() && "Not a use and not a def?");
- ImplicitDefs.set(Op.getImplicitReg());
+ ImplicitDefs.set(Op.getImplicitReg().id());
}
}
}
@@ -300,7 +300,7 @@ ParallelSnippetGenerator::generateCodeTemplates(
Instr.hasMemoryOperands()
? State.getExegesisTarget().getScratchMemoryRegister(
State.getTargetMachine().getTargetTriple())
- : 0;
+ : MCRegister();
const AliasingConfigurations SelfAliasing(Instr, Instr, ForbiddenRegisters);
if (SelfAliasing.empty()) {
CT.Info = "instruction is parallel, repeating a random one.";
diff --git a/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.h b/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.h
index 94eb4e26eb5881..8a6b8569c5d4c0 100644
--- a/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.h
+++ b/llvm/tools/llvm-exegesis/lib/ParallelSnippetGenerator.h
@@ -55,7 +55,7 @@ class ParallelSnippetGenerator : public SnippetGenerator {
// add eax, [rdi + 192]
// mov eax, [rdi + 256]
void instantiateMemoryOperands(
- unsigned ScratchSpaceReg,
+ MCRegister ScratchSpaceReg,
std::vector<InstructionTemplate> &SnippetTemplate) const;
};
diff --git a/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp b/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
index 5c944c90384e3e..0e576fa593fb48 100644
--- a/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
@@ -33,13 +33,13 @@ class ExegesisPowerPCTarget : public ExegesisTarget {
: ExegesisTarget(PPCCpuPfmCounters, PPC_MC::isOpcodeAvailable) {}
private:
- std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override;
bool matchesArch(Triple::ArchType Arch) const override {
return Arch == Triple::ppc64le;
}
- unsigned getScratchMemoryRegister(const Triple &) const override;
- void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+ MCRegister getScratchMemoryRegister(const Triple &) const override;
+ void fillMemoryOperands(InstructionTemplate &IT, MCRegister Reg,
unsigned Offset) const override;
};
} // end anonymous namespace
@@ -55,7 +55,7 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
}
// Generates instruction to load an immediate value into a register.
-static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
+static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
const APInt &Value) {
if (Value.getBitWidth() > RegBitWidth)
llvm_unreachable("Value must fit in the Register");
@@ -67,7 +67,7 @@ static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
.addImm(Value.getZExtValue());
}
-unsigned
+MCRegister
ExegesisPowerPCTarget::getScratchMemoryRegister(const Triple &TT) const {
// R13 is reserved as Thread Pointer, we won't use threading in benchmark, so
// use it as scratch memory register
@@ -75,7 +75,7 @@ ExegesisPowerPCTarget::getScratchMemoryRegister(const Triple &TT) const {
}
void ExegesisPowerPCTarget::fillMemoryOperands(InstructionTemplate &IT,
- unsigned Reg,
+ MCRegister Reg,
unsigned Offset) const {
int MemOpIdx = 0;
if (IT.getInstr().hasTiedRegisters())
@@ -93,7 +93,7 @@ void ExegesisPowerPCTarget::fillMemoryOperands(InstructionTemplate &IT,
}
std::vector<MCInst> ExegesisPowerPCTarget::setRegTo(const MCSubtargetInfo &STI,
- unsigned Reg,
+ MCRegister Reg,
const APInt &Value) const {
// X11 is optional use in function linkage, should be the least used one
// Use it as scratch reg to load immediate.
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 217b423d7b3f33..d70f609c5e0808 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -29,8 +29,8 @@ namespace exegesis {
namespace {
// Stores constant value to a general-purpose (integer) register.
-static std::vector<MCInst> loadIntReg(const MCSubtargetInfo &STI, unsigned Reg,
- const APInt &Value) {
+static std::vector<MCInst> loadIntReg(const MCSubtargetInfo &STI,
+ MCRegister Reg, const APInt &Value) {
SmallVector<MCInst, 8> MCInstSeq;
MCRegister DestReg = Reg;
@@ -40,11 +40,11 @@ static std::vector<MCInst> loadIntReg(const MCSubtargetInfo &STI, unsigned Reg,
return MatIntInstrs;
}
-const unsigned ScratchIntReg = RISCV::X30; // t5
+const MCPhysReg ScratchIntReg = RISCV::X30; // t5
// Stores constant bits to a floating-point register.
static std::vector<MCInst> loadFPRegBits(const MCSubtargetInfo &STI,
- unsigned Reg, const APInt &Bits,
+ MCRegister Reg, const APInt &Bits,
unsigned FmvOpcode) {
std::vector<MCInst> Instrs = loadIntReg(STI, ScratchIntReg, Bits);
Instrs.push_back(MCInstBuilder(FmvOpcode).addReg(Reg).addReg(ScratchIntReg));
@@ -57,7 +57,8 @@ static std::vector<MCInst> loadFPRegBits(const MCSubtargetInfo &STI,
// and then do FCVT this is only reliable thing in 32-bit mode, otherwise we
// need to use __floatsidf
static std::vector<MCInst> loadFP64RegBits32(const MCSubtargetInfo &STI,
- unsigned Reg, const APInt &Bits) {
+ MCRegister Reg,
+ const APInt &Bits) {
double D = Bits.bitsToDouble();
double IPart;
double FPart = std::modf(D, &IPart);
@@ -82,7 +83,7 @@ static MCInst nop() {
.addImm(0);
}
-static bool isVectorRegList(unsigned Reg) {
+static bool isVectorRegList(MCRegister Reg) {
return RISCV::VRM2RegClass.contains(Reg) ||
RISCV::VRM4RegClass.contains(Reg) ||
RISCV::VRM8RegClass.contains(Reg) ||
@@ -105,22 +106,22 @@ class ExegesisRISCVTarget : public ExegesisTarget {
bool matchesArch(Triple::ArchType Arch) const override;
- std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override;
- unsigned getDefaultLoopCounterRegister(const Triple &) const override;
+ MCRegister getDefaultLoopCounterRegister(const Triple &) const override;
void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
MachineBasicBlock &TargetMBB,
const MCInstrInfo &MII,
- unsigned LoopRegister) const override;
+ MCRegister LoopRegister) const override;
- unsigned getScratchMemoryRegister(const Triple &TT) const override;
+ MCRegister getScratchMemoryRegister(const Triple &TT) const override;
- void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+ void fillMemoryOperands(InstructionTemplate &IT, MCRegister Reg,
unsigned Offset) const override;
- ArrayRef<unsigned> getUnavailableRegisters() const override;
+ ArrayRef<MCPhysReg> getUnavailableRegisters() const override;
bool allowAsBackToBack(const Instruction &Instr) const override {
return !Instr.Description.isPseudo();
@@ -143,7 +144,7 @@ bool ExegesisRISCVTarget::matchesArch(Triple::ArchType Arch) const {
}
std::vector<MCInst> ExegesisRISCVTarget::setRegTo(const MCSubtargetInfo &STI,
- unsigned Reg,
+ MCRegister Reg,
const APInt &Value) const {
if (RISCV::GPRRegClass.contains(Reg))
return loadIntReg(STI, Reg, Value);
@@ -173,17 +174,17 @@ std::vector<MCInst> ExegesisRISCVTarget::setRegTo(const MCSubtargetInfo &STI,
return {};
}
-const unsigned DefaultLoopCounterReg = RISCV::X31; // t6
-const unsigned ScratchMemoryReg = RISCV::X10; // a0
+const MCPhysReg DefaultLoopCounterReg = RISCV::X31; // t6
+const MCPhysReg ScratchMemoryReg = RISCV::X10; // a0
-unsigned
+MCRegister
ExegesisRISCVTarget::getDefaultLoopCounterRegister(const Triple &) const {
return DefaultLoopCounterReg;
}
void ExegesisRISCVTarget::decrementLoopCounterAndJump(
MachineBasicBlock &MBB, MachineBasicBlock &TargetMBB,
- const MCInstrInfo &MII, unsigned LoopRegister) const {
+ const MCInstrInfo &MII, MCRegister LoopRegister) const {
BuildMI(&MBB, DebugLoc(), MII.get(RISCV::ADDI))
.addDef(LoopRegister)
.addUse(LoopRegister)
@@ -194,12 +195,13 @@ void ExegesisRISCVTarget::decrementLoopCounterAndJump(
.addMBB(&TargetMBB);
}
-unsigned ExegesisRISCVTarget::getScratchMemoryRegister(const Triple &TT) const {
+MCRegister
+ExegesisRISCVTarget::getScratchMemoryRegister(const Triple &TT) const {
return ScratchMemoryReg; // a0
}
void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,
- unsigned Reg,
+ MCRegister Reg,
unsigned Offset) const {
// TODO: for now we ignore Offset because have no way
// to detect it in instruction.
@@ -217,10 +219,10 @@ void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,
IT.getValueFor(MemOp) = MCOperand::createReg(Reg);
}
-const unsigned UnavailableRegisters[4] = {RISCV::X0, DefaultLoopCounterReg,
- ScratchIntReg, ScratchMemoryReg};
+const MCPhysReg UnavailableRegisters[4] = {RISCV::X0, DefaultLoopCounterReg,
+ ScratchIntReg, ScratchMemoryReg};
-ArrayRef<unsigned> ExegesisRISCVTarget::getUnavailableRegisters() const {
+ArrayRef<MCPhysReg> ExegesisRISCVTarget::getUnavailableRegisters() const {
return UnavailableRegisters;
}
diff --git a/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp b/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
index ee612fb0dd6af6..96040bbf588e52 100644
--- a/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RegisterAliasing.cpp
@@ -39,9 +39,9 @@ RegisterAliasingTracker::RegisterAliasingTracker(
}
RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
- const MCPhysReg PhysReg)
+ const MCRegister PhysReg)
: RegisterAliasingTracker(RegInfo) {
- SourceBits.set(PhysReg);
+ SourceBits.set(PhysReg.id());
FillOriginAndAliasedBits(RegInfo, SourceBits);
}
@@ -63,8 +63,8 @@ RegisterAliasingTrackerCache::RegisterAliasingTrackerCache(
EmptyRegisters(RegInfo.getNumRegs()) {}
const RegisterAliasingTracker &
-RegisterAliasingTrackerCache::getRegister(MCPhysReg PhysReg) const {
- auto &Found = Registers[PhysReg];
+RegisterAliasingTrackerCache::getRegister(MCRegister PhysReg) const {
+ auto &Found = Registers[PhysReg.id()];
if (!Found)
Found.reset(new RegisterAliasingTracker(RegInfo, PhysReg));
return *Found;
diff --git a/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h b/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h
index b2980854ba2d1e..00e699d4c69b9d 100644
--- a/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h
+++ b/llvm/tools/llvm-exegesis/lib/RegisterAliasing.h
@@ -44,9 +44,9 @@ struct RegisterAliasingTracker {
const BitVector &ReservedReg,
const MCRegisterClass &RegClass);
- // Construct a tracker from an MCPhysReg.
+ // Construct a tracker from an MCRegister.
RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
- const MCPhysReg Register);
+ const MCRegister Register);
const BitVector &sourceBits() const { return SourceBits; }
@@ -88,7 +88,7 @@ struct RegisterAliasingTrackerCache {
const MCRegisterInfo ®Info() const { return RegInfo; }
// Retrieves the RegisterAliasingTracker for this particular register.
- const RegisterAliasingTracker &getRegister(MCPhysReg Reg) const;
+ const RegisterAliasingTracker &getRegister(MCRegister Reg) const;
// Retrieves the RegisterAliasingTracker for this particular register class.
const RegisterAliasingTracker &getRegisterClass(unsigned RegClassIndex) const;
diff --git a/llvm/tools/llvm-exegesis/lib/RegisterValue.h b/llvm/tools/llvm-exegesis/lib/RegisterValue.h
index 3429783a48a303..d0f111b9e40e3b 100644
--- a/llvm/tools/llvm-exegesis/lib/RegisterValue.h
+++ b/llvm/tools/llvm-exegesis/lib/RegisterValue.h
@@ -18,14 +18,15 @@
#include <llvm/ADT/APFloat.h>
#include <llvm/ADT/APInt.h>
+#include <llvm/MC/MCRegister.h>
namespace llvm {
namespace exegesis {
// A simple object storing the value for a particular register.
struct RegisterValue {
- static RegisterValue zero(unsigned Reg) { return {Reg, APInt()}; }
- unsigned Register;
+ static RegisterValue zero(MCRegister Reg) { return {Reg, APInt()}; }
+ MCRegister Register;
APInt Value;
};
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp b/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
index b37999ab017f59..01a6e94e76147a 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
@@ -80,7 +80,7 @@ class BenchmarkCodeStreamer : public MCStreamer, public AsmCommentConsumer {
if (CommentText.consume_front("LIVEIN")) {
// LLVM-EXEGESIS-LIVEIN <reg>
const auto RegName = CommentText.ltrim();
- if (unsigned Reg = findRegisterByName(RegName))
+ if (MCRegister Reg = findRegisterByName(RegName))
Result->LiveIns.push_back(Reg);
else {
errs() << "unknown register '" << RegName
@@ -179,7 +179,7 @@ class BenchmarkCodeStreamer : public MCStreamer, public AsmCommentConsumer {
}
if (CommentText.consume_front("LOOP-REGISTER")) {
// LLVM-EXEGESIS-LOOP-REGISTER <loop register>
- unsigned LoopRegister;
+ MCRegister LoopRegister;
if (!(LoopRegister = findRegisterByName(CommentText.trim()))) {
errs() << "unknown register '" << CommentText
@@ -207,13 +207,13 @@ class BenchmarkCodeStreamer : public MCStreamer, public AsmCommentConsumer {
void emitZerofill(MCSection *Section, MCSymbol *Symbol, uint64_t Size,
Align ByteAlignment, SMLoc Loc) override {}
- unsigned findRegisterByName(const StringRef RegName) const {
+ MCRegister findRegisterByName(const StringRef RegName) const {
std::optional<MCRegister> RegisterNumber =
State.getRegisterNumberFromName(RegName);
if (!RegisterNumber.has_value()) {
errs() << "'" << RegName
<< "' is not a valid register name for the target\n";
- return MCRegister::NoRegister;
+ return MCRegister();
}
return *RegisterNumber;
}
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index 48357d443f713e..04064ae1d84410 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -47,9 +47,9 @@ Error SnippetGenerator::generateConfigurations(
// using the scratch register and its aliasing registers.
if (Variant.getInstr().hasMemoryOperands()) {
const auto &ET = State.getExegesisTarget();
- unsigned ScratchSpacePointerInReg =
+ MCRegister ScratchSpacePointerInReg =
ET.getScratchMemoryRegister(State.getTargetMachine().getTargetTriple());
- if (ScratchSpacePointerInReg == 0)
+ if (!ScratchSpacePointerInReg.isValid())
return make_error<Failure>(
"Infeasible : target does not support memory instructions");
const auto &ScratchRegAliases =
@@ -58,7 +58,7 @@ Error SnippetGenerator::generateConfigurations(
// FIXME: We could make a copy of the scratch register.
for (const auto &Op : Variant.getInstr().Operands) {
if (Op.isDef() && Op.isImplicitReg() &&
- ScratchRegAliases.test(Op.getImplicitReg()))
+ ScratchRegAliases.test(Op.getImplicitReg().id()))
return make_error<Failure>(
"Infeasible : memory instruction uses scratch memory register");
}
@@ -114,38 +114,38 @@ std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues(
// If target always expects a scratch memory register as live input,
// mark it as defined.
const ExegesisTarget &Target = State.getExegesisTarget();
- unsigned ScratchMemoryReg = Target.getScratchMemoryRegister(
+ MCRegister ScratchMemoryReg = Target.getScratchMemoryRegister(
State.getTargetMachine().getTargetTriple());
- DefinedRegs.set(ScratchMemoryReg);
+ DefinedRegs.set(ScratchMemoryReg.id());
std::vector<RegisterValue> RIV;
for (const InstructionTemplate &IT : Instructions) {
// Returns the register that this Operand sets or uses, or 0 if this is not
// a register.
- const auto GetOpReg = [&IT](const Operand &Op) -> unsigned {
+ const auto GetOpReg = [&IT](const Operand &Op) -> MCRegister {
if (Op.isMemory())
- return 0;
+ return MCRegister();
if (Op.isImplicitReg())
return Op.getImplicitReg();
if (Op.isExplicit() && IT.getValueFor(Op).isReg())
return IT.getValueFor(Op).getReg();
- return 0;
+ return MCRegister();
};
// Collect used registers that have never been def'ed.
for (const Operand &Op : IT.getInstr().Operands) {
if (Op.isUse()) {
- const unsigned Reg = GetOpReg(Op);
- if (Reg > 0 && !DefinedRegs.test(Reg)) {
+ const MCRegister Reg = GetOpReg(Op);
+ if (Reg && !DefinedRegs.test(Reg.id())) {
RIV.push_back(RegisterValue::zero(Reg));
- DefinedRegs.set(Reg);
+ DefinedRegs.set(Reg.id());
}
}
}
// Mark defs as having been def'ed.
for (const Operand &Op : IT.getInstr().Operands) {
if (Op.isDef()) {
- const unsigned Reg = GetOpReg(Op);
- if (Reg > 0)
- DefinedRegs.set(Reg);
+ const MCRegister Reg = GetOpReg(Op);
+ if (Reg)
+ DefinedRegs.set(Reg.id());
}
}
}
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
index 0bab30d1582003..e4fe27f010c2fb 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp
@@ -48,7 +48,7 @@ class DuplicateSnippetRepetitor : public SnippetRepetitor {
class LoopSnippetRepetitor : public SnippetRepetitor {
public:
- explicit LoopSnippetRepetitor(const LLVMState &State, unsigned LoopRegister)
+ explicit LoopSnippetRepetitor(const LLVMState &State, MCRegister LoopRegister)
: SnippetRepetitor(State), LoopCounter(LoopRegister) {}
// Loop over the snippet ceil(MinInstructions / Instructions.Size()) times.
@@ -102,7 +102,7 @@ class LoopSnippetRepetitor : public SnippetRepetitor {
// The live ins are: the loop counter, the registers that were setup by
// the entry block, and entry block live ins.
Loop.MBB->addLiveIn(LoopCounter);
- for (unsigned Reg : Filler.getRegistersSetUp())
+ for (MCRegister Reg : Filler.getRegistersSetUp())
Loop.MBB->addLiveIn(Reg);
for (const auto &LiveIn : Entry.MBB->liveins())
Loop.MBB->addLiveIn(LiveIn);
@@ -127,7 +127,7 @@ class LoopSnippetRepetitor : public SnippetRepetitor {
}
private:
- const unsigned LoopCounter;
+ const MCRegister LoopCounter;
};
} // namespace
@@ -136,7 +136,7 @@ SnippetRepetitor::~SnippetRepetitor() {}
std::unique_ptr<const SnippetRepetitor>
SnippetRepetitor::Create(Benchmark::RepetitionModeE Mode,
- const LLVMState &State, unsigned LoopRegister) {
+ const LLVMState &State, MCRegister LoopRegister) {
switch (Mode) {
case Benchmark::Duplicate:
case Benchmark::MiddleHalfDuplicate:
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.h b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.h
index c62e80f161f128..88dd0f3cb2dbd0 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.h
+++ b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.h
@@ -30,7 +30,7 @@ class SnippetRepetitor {
public:
static std::unique_ptr<const SnippetRepetitor>
Create(Benchmark::RepetitionModeE Mode, const LLVMState &State,
- unsigned LoopRegister);
+ MCRegister LoopRegister);
virtual ~SnippetRepetitor();
diff --git a/llvm/tools/llvm-exegesis/lib/Target.cpp b/llvm/tools/llvm-exegesis/lib/Target.cpp
index 29e58692f0e92b..5ea5b4c2c002f6 100644
--- a/llvm/tools/llvm-exegesis/lib/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Target.cpp
@@ -212,7 +212,7 @@ class ExegesisDefaultTarget : public ExegesisTarget {
ExegesisDefaultTarget() : ExegesisTarget({}, opcodeIsNotAvailable) {}
private:
- std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override {
llvm_unreachable("Not yet implemented");
}
diff --git a/llvm/tools/llvm-exegesis/lib/Target.h b/llvm/tools/llvm-exegesis/lib/Target.h
index 92cc1cb248a1c0..f3fbe3780616f8 100644
--- a/llvm/tools/llvm-exegesis/lib/Target.h
+++ b/llvm/tools/llvm-exegesis/lib/Target.h
@@ -91,7 +91,8 @@ class ExegesisTarget {
// Generates code to move a constant into a the given register.
// Precondition: Value must fit into Reg.
- virtual std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ virtual std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI,
+ MCRegister Reg,
const APInt &Value) const = 0;
// Generates the code for the lower munmap call. The code generated by this
@@ -177,14 +178,14 @@ class ExegesisTarget {
// Gets the ABI dependent registers that are used to pass arguments in a
// function call.
- virtual std::vector<unsigned> getArgumentRegisters() const {
+ virtual std::vector<MCRegister> getArgumentRegisters() const {
report_fatal_error(
"getArgumentRegisters is not implemented on the current architecture");
};
// Gets the registers that might potentially need to be saved by while
// the setup in the test harness executes.
- virtual std::vector<unsigned> getRegistersNeedSaving() const {
+ virtual std::vector<MCRegister> getRegistersNeedSaving() const {
report_fatal_error("getRegistersNeedSaving is not implemented on the "
"current architecture");
};
@@ -192,25 +193,27 @@ class ExegesisTarget {
// Returns the register pointing to scratch memory, or 0 if this target
// does not support memory operands. The benchmark function uses the
// default calling convention.
- virtual unsigned getScratchMemoryRegister(const Triple &) const { return 0; }
+ virtual MCRegister getScratchMemoryRegister(const Triple &) const {
+ return MCRegister();
+ }
// Fills memory operands with references to the address at [Reg] + Offset.
- virtual void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+ virtual void fillMemoryOperands(InstructionTemplate &IT, MCRegister Reg,
unsigned Offset) const {
llvm_unreachable(
"fillMemoryOperands() requires getScratchMemoryRegister() > 0");
}
// Returns a counter usable as a loop counter.
- virtual unsigned getDefaultLoopCounterRegister(const Triple &) const {
- return 0;
+ virtual MCRegister getDefaultLoopCounterRegister(const Triple &) const {
+ return MCRegister();
}
// Adds the code to decrement the loop counter and
virtual void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
MachineBasicBlock &TargetMBB,
const MCInstrInfo &MII,
- unsigned LoopRegister) const {
+ MCRegister LoopRegister) const {
llvm_unreachable("decrementLoopCounterAndBranch() requires "
"getLoopCounterRegister() > 0");
}
@@ -218,7 +221,7 @@ class ExegesisTarget {
// Returns a list of unavailable registers.
// Targets can use this to prevent some registers to be automatically selected
// for use in snippets.
- virtual ArrayRef<unsigned> getUnavailableRegisters() const { return {}; }
+ virtual ArrayRef<MCPhysReg> getUnavailableRegisters() const { return {}; }
// Returns the maximum number of bytes a load/store instruction can access at
// once. This is typically the size of the largest register available on the
diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
index 3c3bff76fb6812..1659cfb31f117a 100644
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -468,7 +468,7 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
}
// Generates instruction to load an immediate value into a register.
-static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
+static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
const APInt &Value) {
if (Value.getBitWidth() > RegBitWidth)
llvm_unreachable("Value must fit in the Register");
@@ -500,7 +500,7 @@ static MCInst fillStackSpace(unsigned MovOpcode, unsigned OffsetBytes,
}
// Loads scratch memory into register `Reg` using opcode `RMOpcode`.
-static MCInst loadToReg(unsigned Reg, unsigned RMOpcode) {
+static MCInst loadToReg(MCRegister Reg, unsigned RMOpcode) {
return MCInstBuilder(RMOpcode)
.addReg(Reg)
// Address = ESP
@@ -525,12 +525,12 @@ namespace {
struct ConstantInliner {
explicit ConstantInliner(const APInt &Constant) : Constant_(Constant) {}
- std::vector<MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth,
+ std::vector<MCInst> loadAndFinalize(MCRegister Reg, unsigned RegBitWidth,
unsigned Opcode);
- std::vector<MCInst> loadX87STAndFinalize(unsigned Reg);
+ std::vector<MCInst> loadX87STAndFinalize(MCRegister Reg);
- std::vector<MCInst> loadX87FPAndFinalize(unsigned Reg);
+ std::vector<MCInst> loadX87FPAndFinalize(MCRegister Reg);
std::vector<MCInst> popFlagAndFinalize();
@@ -554,7 +554,7 @@ struct ConstantInliner {
};
} // namespace
-std::vector<MCInst> ConstantInliner::loadAndFinalize(unsigned Reg,
+std::vector<MCInst> ConstantInliner::loadAndFinalize(MCRegister Reg,
unsigned RegBitWidth,
unsigned Opcode) {
assert((RegBitWidth & 7) == 0 && "RegBitWidth must be a multiple of 8 bits");
@@ -564,7 +564,7 @@ std::vector<MCInst> ConstantInliner::loadAndFinalize(unsigned Reg,
return std::move(Instructions);
}
-std::vector<MCInst> ConstantInliner::loadX87STAndFinalize(unsigned Reg) {
+std::vector<MCInst> ConstantInliner::loadX87STAndFinalize(MCRegister Reg) {
initStack(kF80Bytes);
add(MCInstBuilder(X86::LD_F80m)
// Address = ESP
@@ -579,7 +579,7 @@ std::vector<MCInst> ConstantInliner::loadX87STAndFinalize(unsigned Reg) {
return std::move(Instructions);
}
-std::vector<MCInst> ConstantInliner::loadX87FPAndFinalize(unsigned Reg) {
+std::vector<MCInst> ConstantInliner::loadX87FPAndFinalize(MCRegister Reg) {
initStack(kF80Bytes);
add(MCInstBuilder(X86::LD_Fp80m)
.addReg(Reg)
@@ -729,9 +729,9 @@ class ExegesisX86Target : public ExegesisTarget {
private:
void addTargetSpecificPasses(PassManagerBase &PM) const override;
- unsigned getScratchMemoryRegister(const Triple &TT) const override;
+ MCRegister getScratchMemoryRegister(const Triple &TT) const override;
- unsigned getDefaultLoopCounterRegister(const Triple &) const override;
+ MCRegister getDefaultLoopCounterRegister(const Triple &) const override;
unsigned getMaxMemoryAccessSize() const override { return 64; }
@@ -739,15 +739,15 @@ class ExegesisX86Target : public ExegesisTarget {
MCOperand &AssignedValue,
const BitVector &ForbiddenRegs) const override;
- void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+ void fillMemoryOperands(InstructionTemplate &IT, MCRegister Reg,
unsigned Offset) const override;
void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
MachineBasicBlock &TargetMBB,
const MCInstrInfo &MII,
- unsigned LoopRegister) const override;
+ MCRegister LoopRegister) const override;
- std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+ std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override;
#ifdef __linux__
@@ -773,12 +773,12 @@ class ExegesisX86Target : public ExegesisTarget {
std::vector<MCInst> configurePerfCounter(long Request, bool SaveRegisters) const override;
- std::vector<unsigned> getArgumentRegisters() const override;
+ std::vector<MCRegister> getArgumentRegisters() const override;
- std::vector<unsigned> getRegistersNeedSaving() const override;
+ std::vector<MCRegister> getRegistersNeedSaving() const override;
#endif // __linux__
- ArrayRef<unsigned> getUnavailableRegisters() const override {
+ ArrayRef<MCPhysReg> getUnavailableRegisters() const override {
if (DisableUpperSSERegisters)
return ArrayRef(kUnavailableRegistersSSE);
@@ -844,25 +844,25 @@ class ExegesisX86Target : public ExegesisTarget {
return std::make_unique<X86SavedState>();
}
- static const unsigned kUnavailableRegisters[4];
- static const unsigned kUnavailableRegistersSSE[12];
+ static const MCPhysReg kUnavailableRegisters[4];
+ static const MCPhysReg kUnavailableRegistersSSE[12];
};
// We disable a few registers that cannot be encoded on instructions with a REX
// prefix.
-const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
- X86::CH, X86::DH};
+const MCPhysReg ExegesisX86Target::kUnavailableRegisters[4] = {
+ X86::AH, X86::BH, X86::CH, X86::DH};
// Optionally, also disable the upper (x86_64) SSE registers to reduce frontend
// decoder load.
-const unsigned ExegesisX86Target::kUnavailableRegistersSSE[12] = {
+const MCPhysReg ExegesisX86Target::kUnavailableRegistersSSE[12] = {
X86::AH, X86::BH, X86::CH, X86::DH, X86::XMM8, X86::XMM9,
X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15};
// We're using one of R8-R15 because these registers are never hardcoded in
// instructions (e.g. MOVS writes to EDI, ESI, EDX), so they have less
// conflicts.
-constexpr const unsigned kDefaultLoopCounterReg = X86::R8;
+constexpr const MCPhysReg kDefaultLoopCounterReg = X86::R8;
} // namespace
@@ -871,19 +871,19 @@ void ExegesisX86Target::addTargetSpecificPasses(PassManagerBase &PM) const {
PM.add(createX86FloatingPointStackifierPass());
}
-unsigned ExegesisX86Target::getScratchMemoryRegister(const Triple &TT) const {
+MCRegister ExegesisX86Target::getScratchMemoryRegister(const Triple &TT) const {
if (!TT.isArch64Bit()) {
// FIXME: This would require popping from the stack, so we would have to
// add some additional setup code.
- return 0;
+ return MCRegister();
}
return TT.isOSWindows() ? X86::RCX : X86::RDI;
}
-unsigned
+MCRegister
ExegesisX86Target::getDefaultLoopCounterRegister(const Triple &TT) const {
if (!TT.isArch64Bit()) {
- return 0;
+ return MCRegister();
}
return kDefaultLoopCounterReg;
}
@@ -910,7 +910,7 @@ Error ExegesisX86Target::randomizeTargetMCOperand(
}
void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
- unsigned Reg,
+ MCRegister Reg,
unsigned Offset) const {
assert(!isInvalidMemoryInstr(IT.getInstr()) &&
"fillMemoryOperands requires a valid memory instruction");
@@ -927,7 +927,7 @@ void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
void ExegesisX86Target::decrementLoopCounterAndJump(
MachineBasicBlock &MBB, MachineBasicBlock &TargetMBB,
- const MCInstrInfo &MII, unsigned LoopRegister) const {
+ const MCInstrInfo &MII, MCRegister LoopRegister) const {
BuildMI(&MBB, DebugLoc(), MII.get(X86::ADD64ri8))
.addDef(LoopRegister)
.addUse(LoopRegister)
@@ -988,7 +988,7 @@ static void restoreSyscallRegisters(std::vector<MCInst> &GeneratedCode,
}
#endif // __linux__
-static std::vector<MCInst> loadImmediateSegmentRegister(unsigned Reg,
+static std::vector<MCInst> loadImmediateSegmentRegister(MCRegister Reg,
const APInt &Value) {
#if defined(__x86_64__) && defined(__linux__)
assert(Value.getBitWidth() <= 64 && "Value must fit in the register.");
@@ -1021,7 +1021,7 @@ static std::vector<MCInst> loadImmediateSegmentRegister(unsigned Reg,
}
std::vector<MCInst> ExegesisX86Target::setRegTo(const MCSubtargetInfo &STI,
- unsigned Reg,
+ MCRegister Reg,
const APInt &Value) const {
if (X86::SEGMENT_REGRegClass.contains(Reg))
return loadImmediateSegmentRegister(Reg, Value);
@@ -1298,11 +1298,11 @@ ExegesisX86Target::configurePerfCounter(long Request, bool SaveRegisters) const
return ConfigurePerfCounterCode;
}
-std::vector<unsigned> ExegesisX86Target::getArgumentRegisters() const {
+std::vector<MCRegister> ExegesisX86Target::getArgumentRegisters() const {
return {X86::RDI, X86::RSI};
}
-std::vector<unsigned> ExegesisX86Target::getRegistersNeedSaving() const {
+std::vector<MCRegister> ExegesisX86Target::getRegistersNeedSaving() const {
return {X86::RAX, X86::RDI, X86::RSI, X86::RCX, X86::R11};
}
diff --git a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
index fa37e05956be8c..b9938a92855a46 100644
--- a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
+++ b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
@@ -520,7 +520,7 @@ void benchmarkMain() {
const auto Opcodes = getOpcodesOrDie(State);
std::vector<BenchmarkCode> Configurations;
- unsigned LoopRegister =
+ MCRegister LoopRegister =
State.getExegesisTarget().getDefaultLoopCounterRegister(
State.getTargetMachine().getTargetTriple());
More information about the llvm-commits
mailing list