[llvm] [NFC][AArch64] Adjust predicate names to be more consistent (PR #123172)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 16 01:28:14 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
<details>
<summary>Changes</summary>
Some of the predicate names use `_or_`, some use plain `or`,
some used `HasXXorHasXX`, some used `HasXX_or_XX`. Make these
as consistent as possible.
---
Patch is 22.84 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/123172.diff
4 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64.td (+7-7)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+12-12)
- (modified) llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+40-40)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 8644264f5fb1c3..84b7b0ab184cb6 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -58,11 +58,11 @@ include "AArch64SystemOperands.td"
class AArch64Unsupported { list<Predicate> F; }
-let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in
+let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_SME2p1] in
def SVE2p1Unsupported : AArch64Unsupported;
def SVE2Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA, HasSMEF8F16,
+ let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4, HasSVEBitPerm,
HasSVEB16B16],
SVE2p1Unsupported.F);
@@ -73,19 +73,19 @@ def SVEUnsupported : AArch64Unsupported {
SVE2Unsupported.F);
}
-let F = [HasSME2p2, HasSVE2p2orSME2p2, HasNonStreamingSVEorSME2p2,
- HasNonStreamingSVE2p2orSME2p2, HasNonStreamingSVE2orSSVE_BitPerm,
+let F = [HasSME2p2, HasSVE2p2_or_SME2p2, HasNonStreamingSVE_or_SME2p2,
+ HasNonStreamingSVE2p2_or_SME2p2, HasNonStreamingSVE2_or_SSVE_BitPerm,
HasSME_MOP4, HasSME_TMOP] in
def SME2p2Unsupported : AArch64Unsupported;
def SME2p1Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSME2p1, HasSVE2p1_or_HasSME2p1, HasNonStreamingSVE2p1orSSVE_AES],
+ let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1, HasNonStreamingSVE2p1_or_SSVE_AES],
SME2p2Unsupported.F);
}
def SME2Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA,
- HasSMEF8F16, HasSMEF8F32, HasSMEF16F16orSMEF8F16, HasSMEB16B16],
+ let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
+ HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16],
SME2p1Unsupported.F);
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 9c7dc7784e9390..55b5a94aa63b75 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -248,49 +248,49 @@ def HasSVEorSME
: Predicate<"Subtarget->hasSVE() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
"sve or sme">;
-def HasNonStreamingSVEorSME2p2
+def HasNonStreamingSVE_or_SME2p2
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
"sve or sme2p2">;
-def HasSVE2orSME
+def HasSVE2_or_SME
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),
"sve2 or sme">;
-def HasSVE2orSME2
+def HasSVE2_or_SME2
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),
"sve2 or sme2">;
-def HasNonStreamingSVE2orSSVE_AES
+def HasNonStreamingSVE2_or_SSVE_AES
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_AES), "sve2 or ssve-aes">;
-def HasSVE2p1_or_HasSME
+def HasSVE2p1_or_SME
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
AssemblerPredicateWithAll<(any_of FeatureSME, FeatureSVE2p1), "sme or sve2p1">;
-def HasSVE2p1_or_HasSME2
+def HasSVE2p1_or_SME2
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1), "sme2 or sve2p1">;
-def HasSVE2p1_or_HasSME2p1
+def HasSVE2p1_or_SME2p1
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2p1())">,
AssemblerPredicateWithAll<(any_of FeatureSME2p1, FeatureSVE2p1), "sme2p1 or sve2p1">;
-def HasSVE2p2orSME2p2
+def HasSVE2p2_or_SME2p2
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2())">,
AssemblerPredicateWithAll<(any_of FeatureSME2p2, FeatureSVE2p2), "sme2p2 or sve2p2">;
-def HasNonStreamingSVE2p1orSSVE_AES
+def HasNonStreamingSVE2p1_or_SSVE_AES
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p1()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2p1, FeatureSSVE_AES), "sve2p1 or ssve-aes">;
-def HasSMEF16F16orSMEF8F16
+def HasSMEF16F16_or_SMEF8F16
: Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">,
AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16),
"sme-f16f16 or sme-f8f16">;
-def HasNonStreamingSVE2p2orSME2p2
+def HasNonStreamingSVE2p2_or_SME2p2
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2p2, FeatureSME2p2),
"sme2p2 or sve2p2">;
-def HasNonStreamingSVE2orSSVE_BitPerm
+def HasNonStreamingSVE2_or_SSVE_BitPerm
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_BitPerm), "sve2 or ssve-bitperm">;
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 98b027862383da..d2aa86f388db20 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -882,7 +882,7 @@ defm LUTI4_S_2ZTZI : sme2p1_luti4_vector_vg2_index<"luti4">;
defm LUTI4_S_4ZTZI : sme2p1_luti4_vector_vg4_index<"luti4">;
}
-let Predicates = [HasSMEF16F16orSMEF8F16] in {
+let Predicates = [HasSMEF16F16_or_SMEF8F16] in {
defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_add_za16_vg1x2>;
defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_add_za16_vg1x4>;
defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_sub_za16_vg1x2>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 22715c61126d1b..f0df1f8b0ee67d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -940,7 +940,7 @@ let Predicates = [HasSVEorSME] in {
} // End HasSVEorSME
// COMPACT - word and doubleword
-let Predicates = [HasNonStreamingSVEorSME2p2] in {
+let Predicates = [HasNonStreamingSVE_or_SME2p2] in {
defm COMPACT_ZPZ : sve_int_perm_compact_sd<"compact", int_aarch64_sve_compact>;
}
@@ -975,7 +975,7 @@ let Predicates = [HasSVEorSME] in {
def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
} // End HasSVEorSME
-let Predicates = [HasNonStreamingSVEorSME2p2] in {
+let Predicates = [HasNonStreamingSVE_or_SME2p2] in {
defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>;
} // End HasSVE
@@ -1172,7 +1172,7 @@ let Predicates = [HasSVEorSME] in {
defm LD2D_IMM : sve_mem_eld_si<0b11, 0b001, ZZ_d, "ld2d", simm4s2>;
defm LD3D_IMM : sve_mem_eld_si<0b11, 0b010, ZZZ_d, "ld3d", simm4s3>;
defm LD4D_IMM : sve_mem_eld_si<0b11, 0b011, ZZZZ_d, "ld4d", simm4s4>;
- let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+ let Predicates = [HasSVE2p1_or_SME2p1] in {
defm LD2Q_IMM : sve_mem_eld_si<0b01, 0b100, ZZ_q, "ld2q", simm4s2>;
defm LD3Q_IMM : sve_mem_eld_si<0b10, 0b100, ZZZ_q, "ld3q", simm4s3>;
defm LD4Q_IMM : sve_mem_eld_si<0b11, 0b100, ZZZZ_q, "ld4q", simm4s4>;
@@ -1191,7 +1191,7 @@ let Predicates = [HasSVEorSME] in {
def LD2D : sve_mem_eld_ss<0b11, 0b101, ZZ_d, "ld2d", GPR64NoXZRshifted64>;
def LD3D : sve_mem_eld_ss<0b11, 0b110, ZZZ_d, "ld3d", GPR64NoXZRshifted64>;
def LD4D : sve_mem_eld_ss<0b11, 0b111, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>;
- let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+ let Predicates = [HasSVE2p1_or_SME2p1] in {
def LD2Q : sve_mem_eld_ss<0b01, 0b001, ZZ_q, "ld2q", GPR64NoXZRshifted128>;
def LD3Q : sve_mem_eld_ss<0b10, 0b001, ZZZ_q, "ld3q", GPR64NoXZRshifted128>;
def LD4Q : sve_mem_eld_ss<0b11, 0b001, ZZZZ_q, "ld4q", GPR64NoXZRshifted128>;
@@ -1638,7 +1638,7 @@ let Predicates = [HasSVEorSME] in {
defm ST2D_IMM : sve_mem_est_si<0b11, 0b01, ZZ_d, "st2d", simm4s2>;
defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>;
defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
- let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+ let Predicates = [HasSVE2p1_or_SME2p1] in {
defm ST2Q_IMM : sve_mem_128b_est_si<0b01, ZZ_q, "st2q", simm4s2>;
defm ST3Q_IMM : sve_mem_128b_est_si<0b10, ZZZ_q, "st3q", simm4s3>;
defm ST4Q_IMM : sve_mem_128b_est_si<0b11, ZZZZ_q, "st4q", simm4s4>;
@@ -1657,7 +1657,7 @@ let Predicates = [HasSVEorSME] in {
def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>;
def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>;
def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>;
- let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+ let Predicates = [HasSVE2p1_or_SME2p1] in {
def ST2Q : sve_mem_128b_est_ss<0b01, ZZ_q, "st2q", GPR64NoXZRshifted128>;
def ST3Q : sve_mem_128b_est_ss<0b10, ZZZ_q, "st3q", GPR64NoXZRshifted128>;
def ST4Q : sve_mem_128b_est_ss<0b11, ZZZZ_q, "st4q", GPR64NoXZRshifted128>;
@@ -3505,7 +3505,7 @@ let Predicates = [HasSVEorSME, HasMatMulFP64] in {
defm TRN2_ZZZ_Q : sve_int_perm_bin_perm_128_zz<0b11, 1, "trn2", int_aarch64_sve_trn2q>;
} // End HasSVEorSME, HasMatMulFP64
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 integer multiply-add (indexed)
defm MLA_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b0, "mla", int_aarch64_sve_mla_lane>;
defm MLS_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b1, "mls", int_aarch64_sve_mls_lane>;
@@ -3653,17 +3653,17 @@ let Predicates = [HasSVE2orSME] in {
defm UQSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd<int_aarch64_sve_uqshl>;
defm SQRSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd<int_aarch64_sve_sqrshl>;
defm UQRSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd<int_aarch64_sve_uqrshl>;
-} // End HasSVE2orSME
+} // End HasSVE2_or_SME
-let Predicates = [HasSVE2orSME, UseExperimentalZeroingPseudos] in {
+let Predicates = [HasSVE2_or_SME, UseExperimentalZeroingPseudos] in {
defm SQSHL_ZPZI : sve_int_bin_pred_shift_imm_left_zeroing_bhsd<null_frag>;
defm UQSHL_ZPZI : sve_int_bin_pred_shift_imm_left_zeroing_bhsd<null_frag>;
defm SRSHR_ZPZI : sve_int_bin_pred_shift_imm_right_zeroing_bhsd<int_aarch64_sve_srshr>;
defm URSHR_ZPZI : sve_int_bin_pred_shift_imm_right_zeroing_bhsd<int_aarch64_sve_urshr>;
defm SQSHLU_ZPZI : sve_int_bin_pred_shift_imm_left_zeroing_bhsd<int_aarch64_sve_sqshlu>;
-} // End HasSVE2orSME, UseExperimentalZeroingPseudos
+} // End HasSVE2_or_SME, UseExperimentalZeroingPseudos
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left_dup<0b0110, "sqshl", "SQSHL_ZPZI", int_aarch64_sve_sqshl>;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left_dup<0b0111, "uqshl", "UQSHL_ZPZI", int_aarch64_sve_uqshl>;
@@ -3776,7 +3776,7 @@ let Predicates = [HasSVE2orSME] in {
defm SQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b00, "sqxtnt", int_aarch64_sve_sqxtnt>;
defm UQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b01, "uqxtnt", int_aarch64_sve_uqxtnt>;
defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow_top<0b10, "sqxtunt", int_aarch64_sve_sqxtunt>;
-} // End HasSVE2orSME
+} // End HasSVE2_or_SME
let Predicates = [HasSVE2] in {
// SVE2 character match
@@ -3784,7 +3784,7 @@ let Predicates = [HasSVE2] in {
defm NMATCH_PPzZZ : sve2_char_match<0b1, "nmatch", int_aarch64_sve_nmatch>;
} // End HasSVE2
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 bitwise exclusive-or interleaved
defm EORBT_ZZZ : sve2_bitwise_xor_interleaved<0b0, "eorbt", int_aarch64_sve_eorbt>;
defm EORTB_ZZZ : sve2_bitwise_xor_interleaved<0b1, "eortb", int_aarch64_sve_eortb>;
@@ -3799,7 +3799,7 @@ let Predicates = [HasSVE2orSME] in {
defm SADDLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b00, "saddlbt", int_aarch64_sve_saddlbt>;
defm SSUBLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b10, "ssublbt", int_aarch64_sve_ssublbt>;
defm SSUBLTB_ZZZ : sve2_misc_int_addsub_long_interleaved<0b11, "ssubltb", int_aarch64_sve_ssubltb>;
-} // End HasSVE2orSME
+} // End HasSVE2_or_SME
let Predicates = [HasSVE2] in {
// SVE2 histogram generation (segment)
@@ -3809,16 +3809,16 @@ let Predicates = [HasSVE2] in {
defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt", int_aarch64_sve_histcnt>;
} // End HasSVE2
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 floating-point base 2 logarithm as integer
defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb", "FLOGB_ZPZZ", int_aarch64_sve_flogb>;
}
-let Predicates = [HasSVE2orSME, UseExperimentalZeroingPseudos] in {
+let Predicates = [HasSVE2_or_SME, UseExperimentalZeroingPseudos] in {
defm FLOGB_ZPZZ : sve2_fp_un_pred_zeroing_hsd<int_aarch64_sve_flogb>;
-} // End HasSVE2orSME, UseExperimentalZeroingPseudos
+} // End HasSVE2_or_SME, UseExperimentalZeroingPseudos
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 floating-point convert precision
defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding_top<"fcvtxnt", "int_aarch64_sve_fcvtxnt">;
defm FCVTX_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtx", "int_aarch64_sve_fcvtx", AArch64fcvtx_mt>;
@@ -3861,7 +3861,7 @@ let Predicates = [HasSVE2orSME] in {
def : Pat<(nxv16i8 (AArch64ext nxv16i8:$zn1, nxv16i8:$zn2, (i32 imm0_255:$imm))),
(EXT_ZZI_B (REG_SEQUENCE ZPR2, $zn1, zsub0, $zn2, zsub1), imm0_255:$imm)>;
}
-} // End HasSVE2orSME
+} // End HasSVE2_or_SME
let Predicates = [HasSVE2] in {
// SVE2 non-temporal gather loads
@@ -3880,10 +3880,10 @@ let Predicates = [HasSVE2] in {
defm LDNT1D_ZZR_D : sve2_mem_gldnt_vs_64_ptrs<0b11110, "ldnt1d", AArch64ldnt1_gather_z, nxv2i64>;
} // End HasSVE2
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 vector splice (constructive)
defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice", AArch64splice>;
-} // End HasSVE2orSME
+} // End HasSVE2_or_SME
let Predicates = [HasSVE2] in {
// SVE2 non-temporal scatter stores
@@ -3897,7 +3897,7 @@ let Predicates = [HasSVE2] in {
defm STNT1D_ZZR_D : sve2_mem_sstnt_vs_64_ptrs<0b110, "stnt1d", AArch64stnt1_scatter, nxv2i64>;
} // End HasSVE2
-let Predicates = [HasSVE2orSME] in {
+let Predicates = [HasSVE2_or_SME] in {
// SVE2 table lookup (three sources)
defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl", int_aarch64_sve_tbl2>;
defm TBX_ZZZ : sve2_int_perm_tbx<"tbx", 0b01, int_aarch64_sve_tbx>;
@@ -3916,9 +3916,9 @@ let Predicates = [HasSVE2orSME] in {
// SVE2 pointer conflict compare
defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr", "int_aarch64_sve_whilewr">;
defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw", "int_aarch64_sve_whilerw">;
-} // End HasSVE2orSME
+} // End HasSVE2_or_SME
-let Predicates = [HasSVEAES, HasNonStreamingSVE2orSSVE_AES] in {
+let Predicates = [HasSVEAES, HasNonStreamingSVE2_or_SSVE_AES] in {
// SVE2 crypto destructive binary operations
defm AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8, int_aarch64_sve_aese, nxv16i8>;
defm AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8, int_aarch64_sve_aesd, nxv16i8>;
@@ -3946,14 +3946,14 @@ let Predicates = [HasSVE2SHA3] in {
defm RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64, int_aarch64_sve_rax1, nxv2i64>;
} // End HasSVE2SHA3
-let Predicates = [HasSVEBitPerm, HasNonStreamingSVE2orSSVE_BitPerm] in {
+let Predicates = [HasSVEBitPerm, HasNonStreamingSVE2_or_SSVE_BitPerm] in {
// SVE2 bitwise permute
defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext", int_aarch64_sve_bext_x>;
defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep", int_aarch64_sve_bdep_x>;
defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp", int_aarch64_sve_bgrp_x>;
}
-let Predicates = [HasSVEAES2, HasNonStreamingSVE2p1orSSVE_AES] in {
+let Predicates = [HasSVEAES2, HasNonStreamingSVE2p1_or_SSVE_AES] in {
// SVE_AES2 multi-vector instructions (x2)
def AESE_2ZZI_B : sve_crypto_binary_multi2<0b000, "aese">;
def AESD_2ZZI_B : sve_crypto_binary_multi2<0b010, "aesd">;
@@ -3974,20 +3974,20 @@ let Predicates = [HasSVEAES2, HasNonStreamingSVE2p1orSSVE_AES] in {
// SME or SVE2.1 instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasSVE2p1_or_HasSME] in {
+let Predicates = [HasSVE2p1_or_SME] in {
defm REVD_ZPmZ : sve2_int_perm_revd<"revd", AArch64revd_mt>;
defm SCLAMP_ZZZ : sve2_clamp<"sclamp", 0b0, AArch64sclamp>;
defm UCLAMP_ZZZ : sve2_clamp<"uclamp", 0b1, AArch64uclamp>;
defm PSEL_PPPRI : sve2_int_perm_sel_p<"psel", int_aarch64_sve_psel>;
-} // End HasSVE2p1_or_HasSME
+} // End HasSVE2p1_or_SME
//===----------------------------------------------------------------------===//
// SME2 or SVE2.1 instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasSVE2p1_or_HasSME2] in {
+let Predicates = [HasSVE2p1_or_SME2] in {
defm FCLAMP_ZZZ : sve_fp_clamp<"fclamp", AArch64fclamp>;
defm FDOT_ZZZ_S : sve_float_dot<0b0, 0b0, ZPR32, ZPR16, "fdot", nxv8f16, int_aarch64_sve_fdot_x2>;
@@ -4154,7 +4154,7 @@ defm WHILEHS_CXX : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
defm WHILEHI_CXX : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
-} // End HasSVE2p1_or_HasSME2
+} // End HasSVE2p1_or_SME2
let Predicates = [HasSVEorSME] in {
@@ -4222,7 +4222,7 @@ let Predicates = [HasSVEBFSCALE] in {
//===----------------------------------------------------------------------===//
// SME2.1 or SVE2.1 instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasSVE2p1_or_HasSME2p1] in {
+let Predicates = [HasSVE2p1_or_SME2p1] in {
defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv", int_aarch64_sve_faddqv>;
defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv", int_aarch64_sve_fmaxnmqv>;
defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv", int_aarch64_sve_fminnmqv>;
@@ -4250,13 +4250,13 @@ defm UZPQ1_ZZZ : sve2p1_permute_vec_elems_q<0b010, "uzpq1", int_aarch64_sve_uzpq
defm UZPQ2_ZZZ : sve2p1_permute_vec_elems_q<0b011, "uzpq2", int_aarch64_sve_uzpq2>;
defm TBXQ_ZZZ : sve2_int_perm_tbx<"tbxq", 0b10, int_aarch64_sve_tbxq>;
defm TBLQ_ZZZ : sve2p1_tblq<"tblq", int_aarch64_sve_tblq>;
-} // End HasSVE2p1_or_HasSME2p1
+} // End HasSVE2p1_or_SME2p1
//===----------------------------------------------------------------------===//
// SME2.2 or SVE2.2 instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasSVE2p2orSME2p2] in {
+let Predicates = [HasSVE2p2_or_SME2p2] in {
// SVE Floating-point convert precision, zeroing predicate
defm FCVT_ZPzZ : ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/123172
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