[llvm] [AMDGPU] Disable VALU sinking and hoisting with WWM (PR #123124)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

> Missing new test?

Yes. I have spent today 3 hours trying to reproduce the original problem in a reasonably small and clear testcase and failed so far. I can create a small mir testcase, not clear as well due to the pass pipeline differences between llc and llpc, plus testcase showing the property is added to the MFI, but I really want to hear from gfx if that is a welcomed approach at all. The gfx here is essential because the problem really happens when atomic optimizer is run. It is disabled for compute but enabled for llpc. I am not aware of any other scenario for compute when a strict.wwm call will happen, and will happen late enough for an IR LICM to miss it.

https://github.com/llvm/llvm-project/pull/123124