[llvm] [AMDGPU] Fix unreachable reg bit width (PR #122107)

[Jun Wang via llvm-commits]

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@@ -0,0 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=early-machinelicm -run-pass=postmisched -o - %s | FileCheck %s
+---
+name:            test_xnull_256
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jwanggit86 wrote:

The original problem was triggered by SReg_256_XNULL. So maybe we just fix it for that reg class?

https://github.com/llvm/llvm-project/pull/122107