[llvm] [AArch64] Use spill size when calculating SVE callee saves size (NFC) (PR #123086)

[Benjamin Maxwell via llvm-commits]

https://github.com/MacDue created https://github.com/llvm/llvm-project/pull/123086

This is an NFC right now, as currently, all SVE register and spill sizes are the same, but the spill size is the correct size to use here.

>From 4fa0b0d2cbe9aaa6615a66b65a51aacc20d521bd Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Wed, 15 Jan 2025 16:50:01 +0000
Subject: [PATCH] [AArch64] Use spill size when calculating SVE callee saves
 size (NFC)

This is an NFC right now, as currently, all SVE register and spill sizes
are the same, but the spill size is the correct size to use here.
---
 llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 206e410047db56..dd248cf39a5ce9 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3795,14 +3795,15 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   unsigned CSStackSize = 0;
   unsigned SVECSStackSize = 0;
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
-  const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (unsigned Reg : SavedRegs.set_bits()) {
-    auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
+    auto *RC = TRI->getMinimalPhysRegClass(Reg);
+    assert(RC && "expected register class!");
+    auto SpillSize = TRI->getSpillSize(*RC);
     if (AArch64::PPRRegClass.contains(Reg) ||
         AArch64::ZPRRegClass.contains(Reg))
-      SVECSStackSize += RegSize;
+      SVECSStackSize += SpillSize;
     else
-      CSStackSize += RegSize;
+      CSStackSize += SpillSize;
   }
 
   // Increase the callee-saved stack size if the function has streaming mode