[llvm] [AMDGPU] select v_sat_pk from two i16 or v2i16 (PR #121124)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 14 19:07:43 PST 2025
https://github.com/Shoreshen updated https://github.com/llvm/llvm-project/pull/121124
>From ab0d61429fbacd122fd147f3ba85a4a8c5f3e3d7 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 10:00:33 +0800
Subject: [PATCH 1/9] select v_sat_pk from 2 i16
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 14 ++++++++++++++
llvm/lib/Target/AMDGPU/SIInstructions.td | 12 ++++++++++++
2 files changed, 26 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 6a5065cd4a0e8f..0a7747b8736786 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -315,6 +315,20 @@ def srl_16 : PatFrag<
(ops node:$src0), (srl_oneuse node:$src0, (i32 16))
>;
+def clamp_s16_u8 : PatFrag<
+ (ops node:$src),
+ (i16 (AMDGPUsmed3 $src, (i16 0), (i16 255)))
+>;
+
+def conc_lo_u8_i16 : PatFrags<
+ (ops node:$src0, node:$src1),
+ [
+ (or
+ (and (i16 $src0), (i16 255)),
+ (shl (i16 $src1), (i16 8))
+ )
+ ]
+>;
def hi_i16_elt : PatFrag<
(ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index cdc1132579d8d8..4ccb168368030b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3298,6 +3298,18 @@ def : GCNPat <
(v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
>;
+multiclass V_SAT_PK_Pat<Instruction inst> {
+ def: GCNPat<
+ (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
+ (inst
+ (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ >;
+}
+
+let OtherPredicates = [NotHasTrue16BitInsts] in
+defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_e64>;
+
// With multiple uses of the shift, this will duplicate the shift and
// increase register pressure.
def : GCNPat <
>From 8ca654f6bcfb306596f4927bb586dd8060e24f45 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 12:49:27 +0800
Subject: [PATCH 2/9] add test, update pattern
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 0a7747b8736786..79a68c9c452ae6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -324,7 +324,7 @@ def conc_lo_u8_i16 : PatFrags<
(ops node:$src0, node:$src1),
[
(or
- (and (i16 $src0), (i16 255)),
+ (i16 $src0),
(shl (i16 $src1), (i16 8))
)
]
>From e8d88baf59f5898d60c5775af76cef2dd8f2f88a Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 19:09:36 +0800
Subject: [PATCH 3/9] add more cases and patters
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 39 ++++++++++++++++----
llvm/lib/Target/AMDGPU/SIInstructions.td | 24 +++++++++---
2 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 79a68c9c452ae6..918ea19276dcbd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -321,13 +321,38 @@ def clamp_s16_u8 : PatFrag<
>;
def conc_lo_u8_i16 : PatFrags<
- (ops node:$src0, node:$src1),
- [
- (or
- (i16 $src0),
- (shl (i16 $src1), (i16 8))
- )
- ]
+ (ops node:$src0, node:$src1),
+ [
+ (or
+ (i16 $src0),
+ (shl (i16 $src1), (i16 8))
+ ),
+ (or
+ (and (i16 $src0), (i16 255)),
+ (shl (i16 $src1), (i16 8))
+ ),
+ ]
+>;
+
+def clamp_v2i16_u8 : PatFrags<
+ (ops node:$src),
+ [
+ (v2i16 (smax (smin $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0)))),
+ (v2i16 (smin (smax $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0))))
+ ]
+>;
+
+def conc_lo_v2i16_i16 : PatFrags<
+ (ops node:$src),
+ [
+ (or
+ (i16 (trunc (i32 (bitconvert $src)))),
+ (shl
+ (i16 (trunc(srl (i32 (bitconvert $src)), (i32 16)))),
+ (i16 8)
+ )
+ )
+ ]
>;
def hi_i16_elt : PatFrag<
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 4ccb168368030b..53e4908c145095 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3299,12 +3299,24 @@ def : GCNPat <
>;
multiclass V_SAT_PK_Pat<Instruction inst> {
- def: GCNPat<
- (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
- (inst
- (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
- (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
- >;
+ def: GCNPat<
+ (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
+ (inst
+ (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ >;
+
+ def: GCNPat<
+ (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
+ (inst
+ (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ >;
+
+ def: GCNPat<
+ (i16 (conc_lo_v2i16_i16 (clamp_v2i16_u8 v2i16:$src))),
+ (inst VGPR_32:$src)
+ >;
}
let OtherPredicates = [NotHasTrue16BitInsts] in
>From 889198d6c3482ee41b9e707324f308d596df51eb Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 23:14:26 +0800
Subject: [PATCH 4/9] fix bug and add case
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 2 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 918ea19276dcbd..230c2fff5f3196 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -338,7 +338,7 @@ def clamp_v2i16_u8 : PatFrags<
(ops node:$src),
[
(v2i16 (smax (smin $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0)))),
- (v2i16 (smin (smax $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0))))
+ (v2i16 (smin (smax $src, (build_vector (i16 0), (i16 0))), (build_vector (i16 255), (i16 255))))
]
>;
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 2d84e877229515..947ac9be8c9cfe 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -1390,3 +1390,5 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
ret i16 %cast
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
>From 582c56a3ab7055cd7ff879b1fd21125a131ccd20 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Sat, 28 Dec 2024 20:44:04 +0800
Subject: [PATCH 5/9] fix globalisel, merge main
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 12 +++++++++++-
llvm/lib/Target/AMDGPU/SIInstructions.td | 11 +++++++----
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 14 ++------------
3 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 230c2fff5f3196..3e094de311d522 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -330,7 +330,7 @@ def conc_lo_u8_i16 : PatFrags<
(or
(and (i16 $src0), (i16 255)),
(shl (i16 $src1), (i16 8))
- ),
+ )
]
>;
@@ -351,6 +351,16 @@ def conc_lo_v2i16_i16 : PatFrags<
(i16 (trunc(srl (i32 (bitconvert $src)), (i32 16)))),
(i16 8)
)
+ ),
+ (or
+ (and (i16 (trunc (i32 (bitconvert $src)))), (i16 255)),
+ (shl
+ (and
+ (i16 (trunc (srl (i32 (bitconvert $src)), (i32 16)))),
+ (i16 255)
+ ),
+ (i16 8)
+ )
)
]
>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 53e4908c145095..b60e454c40d298 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -10,7 +10,10 @@
// that are not yet supported remain commented out.
//===----------------------------------------------------------------------===//
-class GCNPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl;
+class GCNPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl, GISelFlags;
+
+let GIIgnoreCopies = 1 in
+class GCNPatIgnoreCopies<dag pattern, dag result> : GCNPat<pattern, result>;
class UniformSextInreg<ValueType VT> : PatFrag<
(ops node:$src),
@@ -3299,21 +3302,21 @@ def : GCNPat <
>;
multiclass V_SAT_PK_Pat<Instruction inst> {
- def: GCNPat<
+ def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
(inst
(V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
(V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
>;
- def: GCNPat<
+ def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
(inst
(V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
(V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
>;
- def: GCNPat<
+ def: GCNPatIgnoreCopies<
(i16 (conc_lo_v2i16_i16 (clamp_v2i16_u8 v2i16:$src))),
(inst VGPR_32:$src)
>;
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 947ac9be8c9cfe..596b1561348af5 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -1226,12 +1226,7 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; GISEL-GFX9-LABEL: basic_smax_smin_vec_input:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff00ff
-; GISEL-GFX9-NEXT: v_pk_min_i16 v0, v1, v0
-; GISEL-GFX9-NEXT: v_pk_max_i16 v0, 0, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff
-; GISEL-GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GISEL-GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_smax_smin_vec_input:
@@ -1341,12 +1336,7 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; GISEL-GFX9-LABEL: basic_smax_smin_vec_input_rev:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT: v_pk_max_i16 v0, 0, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff00ff
-; GISEL-GFX9-NEXT: v_pk_min_i16 v0, v1, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff
-; GISEL-GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GISEL-GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_smax_smin_vec_input_rev:
>From 5319c9f53c4b0890b5366c3ffe4282192869768f Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Tue, 7 Jan 2025 17:18:01 +0800
Subject: [PATCH 6/9] add v_sat_pk pattern for fake16, add test cases for
GFX12, merge main
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 8 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 98 +++++++++++----------
2 files changed, 57 insertions(+), 49 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index b60e454c40d298..520680311a8aca 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3318,12 +3318,14 @@ multiclass V_SAT_PK_Pat<Instruction inst> {
def: GCNPatIgnoreCopies<
(i16 (conc_lo_v2i16_i16 (clamp_v2i16_u8 v2i16:$src))),
- (inst VGPR_32:$src)
+ (inst VRegSrc_32:$src)
>;
}
-let OtherPredicates = [NotHasTrue16BitInsts] in
-defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_e64>;
+let OtherPredicates = [NotHasTrue16BitInsts] in {
+ defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_e64>;
+} // End OtherPredicates = [NotHasTrue16BitInsts]
+defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_fake16_e64>;
// With multiple uses of the shift, this will duplicate the shift and
// increase register pressure.
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 596b1561348af5..10cb11494c7cb2 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -839,6 +839,19 @@ define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
; SDAG-GFX12-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
+; SDAG-GFX12-LABEL: basic_smax_smin_bit_or:
+; SDAG-GFX12: ; %bb.0:
+; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-VI-LABEL: basic_smax_smin_bit_or:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -926,6 +939,20 @@ define i16 @basic_umax_umin_bit_or(i16 %src0, i16 %src1) {
; SDAG-GFX12-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
+; SDAG-GFX12-LABEL: basic_umax_umin_bit_or:
+; SDAG-GFX12: ; %bb.0:
+; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT: v_min_u16 v1, 0xff, v1
+; SDAG-GFX12-NEXT: v_min_u16 v0, 0xff, v0
+; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX12-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX12-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-VI-LABEL: basic_umax_umin_bit_or:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -992,13 +1019,10 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
; SDAG-GFX11-LABEL: basic_smax_smin_vec_cast:
; SDAG-GFX11: ; %bb.0:
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
-; SDAG-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
-; SDAG-GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-LABEL: basic_smax_smin_vec_cast:
@@ -1041,11 +1065,10 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
; GISEL-GFX11-LABEL: basic_smax_smin_vec_cast:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
-; GISEL-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
-; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-LABEL: basic_smax_smin_vec_cast:
@@ -1117,6 +1140,19 @@ define i16 @basic_smax_smin_bit_shl(i16 %src0, i16 %src1) {
; SDAG-GFX12-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
+; SDAG-GFX12-LABEL: basic_smax_smin_bit_shl:
+; SDAG-GFX12: ; %bb.0:
+; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
+; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
+; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
+; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
+; SDAG-GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-VI-LABEL: basic_smax_smin_bit_shl:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1185,13 +1221,7 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; SDAG-GFX11-LABEL: basic_smax_smin_vec_input:
; SDAG-GFX11: ; %bb.0:
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_pk_max_i16 v0, v0, 0
-; SDAG-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
-; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-LABEL: basic_smax_smin_vec_input:
@@ -1232,16 +1262,7 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; GISEL-GFX11-LABEL: basic_smax_smin_vec_input:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_pk_min_i16 v0, 0xff00ff, v0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_pk_max_i16 v0, 0, v0
-; GISEL-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-LABEL: basic_smax_smin_vec_input:
@@ -1296,13 +1317,7 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; SDAG-GFX11-LABEL: basic_smax_smin_vec_input_rev:
; SDAG-GFX11: ; %bb.0:
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_pk_max_i16 v0, v0, 0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
-; SDAG-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
-; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX12-LABEL: basic_smax_smin_vec_input_rev:
@@ -1342,16 +1357,7 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; GISEL-GFX11-LABEL: basic_smax_smin_vec_input_rev:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_pk_max_i16 v0, 0, v0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_pk_min_i16 v0, 0xff00ff, v0
-; GISEL-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-LABEL: basic_smax_smin_vec_input_rev:
>From fe7c1c7ffb167bec0bafe5137e649f031d41cdc1 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Tue, 7 Jan 2025 17:40:36 +0800
Subject: [PATCH 7/9] change to VRegSrc_32
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 520680311a8aca..19471a55934bfd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3305,15 +3305,15 @@ multiclass V_SAT_PK_Pat<Instruction inst> {
def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
(inst
- (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
- (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ (V_LSHL_OR_B32_e64 VRegSrc_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VRegSrc_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
>;
def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
(inst
- (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
- (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ (V_LSHL_OR_B32_e64 VRegSrc_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VRegSrc_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
>;
def: GCNPatIgnoreCopies<
>From 52498241aa0d7789a837e8b3e9605a37e0261d61 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Wed, 8 Jan 2025 10:39:41 +0800
Subject: [PATCH 8/9] do not clamp && merge main
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 4 ++--
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 12 ++++--------
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 19471a55934bfd..4b06fae0514773 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3306,14 +3306,14 @@ multiclass V_SAT_PK_Pat<Instruction inst> {
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
(inst
(V_LSHL_OR_B32_e64 VRegSrc_32:$hi, (S_MOV_B32 (i32 16)),
- (V_AND_B32_e64 VRegSrc_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ VRegSrc_32:$lo))
>;
def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
(inst
(V_LSHL_OR_B32_e64 VRegSrc_32:$hi, (S_MOV_B32 (i32 16)),
- (V_AND_B32_e64 VRegSrc_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ VRegSrc_32:$lo))
>;
def: GCNPatIgnoreCopies<
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 10cb11494c7cb2..7bd666aad08c82 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -846,9 +846,8 @@ define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX12-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -1019,9 +1018,8 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
; SDAG-GFX11-LABEL: basic_smax_smin_vec_cast:
; SDAG-GFX11: ; %bb.0:
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1065,9 +1063,8 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
; GISEL-GFX11-LABEL: basic_smax_smin_vec_cast:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX11-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1147,9 +1144,8 @@ define i16 @basic_smax_smin_bit_shl(i16 %src0, i16 %src1) {
; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX12-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX12-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
;
>From 0e4c4ed580caa60f26f2f56444cf427f767a9087 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 9 Jan 2025 11:56:34 +0800
Subject: [PATCH 9/9] add predicate for fake16 inst
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 4b06fae0514773..eba5b160714c88 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3325,7 +3325,9 @@ multiclass V_SAT_PK_Pat<Instruction inst> {
let OtherPredicates = [NotHasTrue16BitInsts] in {
defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_e64>;
} // End OtherPredicates = [NotHasTrue16BitInsts]
-defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_fake16_e64>;
+let True16Predicate = UseFakeTrue16Insts in {
+ defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_fake16_e64>;
+}
// With multiple uses of the shift, this will duplicate the shift and
// increase register pressure.
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