[llvm] [AMDGPU] Set Convergent property for image.(getlod/sample*) intrinsics which uses WQM (PR #122908)
Mariusz Sikora via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 14 12:44:01 PST 2025
https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/122908
>From be94d5850a2226b73282b886e74d66112f88cdbc Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Tue, 14 Jan 2025 03:30:35 -0500
Subject: [PATCH 1/2] [AMDGPU] Set Convergent property for
image.(getlod/sample*) intrinsics which uses WQM
This change adds IntrConvergent property to image.getlod intrinsic and
to several image.sample intrinsics. All image.sample intrinsics apart
from LOD(_L), Level 0(_LZ), Derivative(_D) will be marked as Convergent.
---
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 11 ++++++++---
llvm/test/CodeGen/AMDGPU/sink-image-sample.ll | 4 ++--
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index b930d6983e2251..b529642a558710 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -876,6 +876,8 @@ class AMDGPUSampleVariant<string ucmod, string lcmod, list<AMDGPUArg> extra_addr
// Name of the {lod} or {clamp} argument that is appended to the coordinates,
// if any.
string LodOrClamp = "";
+
+ bit UsesWQM = false;
}
// AMDGPUSampleVariants: all variants supported by IMAGE_SAMPLE
@@ -905,8 +907,9 @@ defset list<AMDGPUSampleVariant> AMDGPUSampleVariants = {
}
defset list<AMDGPUSampleVariant> AMDGPUSampleVariantsNoGradients = {
+ let UsesWQM = true in
defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"", "", []>;
- let Bias = true in
+ let Bias = true, UsesWQM = true in
defm AMDGPUSample : AMDGPUSampleHelper_Clamp<
"_B", "_b", [AMDGPUArg<llvm_anyfloat_ty, "bias">]>;
let LodOrClamp = "lod" in
@@ -1172,7 +1175,8 @@ defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = {
foreach dim = AMDGPUDims.NoMsaa in {
def !strconcat(NAME, "_", dim.Name) : AMDGPUImageDimIntrinsic<
AMDGPUDimSampleProfile<opmod, dim, sample>,
- !if(NoMem, [IntrNoMem], [IntrReadMem]),
+ !listconcat(!if(NoMem, [IntrNoMem], [IntrReadMem]),
+ !if(sample.UsesWQM, [IntrConvergent], [])),
!if(NoMem, [], [SDNPMemOperand])>;
}
}
@@ -1188,7 +1192,8 @@ defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = {
foreach dim = AMDGPUDims.NoMsaa in {
def !strconcat(NAME, "_", dim.Name, "_nortn") : AMDGPUImageDimIntrinsic<
AMDGPUDimSampleNoReturnProfile<opmod, dim, sample>,
- [IntrWillReturn], [SDNPMemOperand]>;
+ !listconcat([IntrWillReturn], !if(sample.UsesWQM, [IntrConvergent], [])),
+ [SDNPMemOperand]>;
}
}
foreach sample = AMDGPUSampleVariants in {
diff --git a/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll b/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
index e1273e1a4bcd08..8a3b544ac2b80f 100644
--- a/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
+++ b/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
@@ -11,7 +11,7 @@
define amdgpu_ps float @sinking_img_sample() {
main_body:
- %i = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
+ %i = call <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 7, float undef, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
br i1 undef, label %endif1, label %if1
if1: ; preds = %main_body
@@ -28,7 +28,7 @@ exit: ; preds = %endif1, %if1
ret float %i24
}
; Function Attrs: nounwind readonly willreturn
-declare <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
declare float @llvm.fma.f32(float, float, float) #2
>From 4699392d7a3743bf297ae7f75448c6ef705ee30c Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Tue, 14 Jan 2025 12:44:05 -0500
Subject: [PATCH 2/2] Add more tests for image sample
---
llvm/test/CodeGen/AMDGPU/sink-image-sample.ll | 127 ++++++++++++++++--
1 file changed, 118 insertions(+), 9 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll b/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
index 8a3b544ac2b80f..eb8c3cadc49978 100644
--- a/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
+++ b/llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
@@ -1,34 +1,143 @@
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
-; Test that image.sample instruction is sunk across the branch and not left in the first block. Since the kill may terminate the shader there might be no need for sampling the image.
+; Test that image.sample LOD(_L), Level 0(_LZ), Derivative(_D) instructions are sunk across the branch and not left in the first block. Since the kill may terminate the shader there might be no need for sampling the image.
; GCN-LABEL: {{^}}sinking_img_sample:
-; GCN-NOT: image_sample
+; GCN-NOT: image_sample_l v
+; GCN-NOT: image_sample_lz v
+; GCN-NOT: image_sample_c_lz v
+; GCN-NOT: image_sample_c_l v
+; GCN-NOT: image_sample_d v
+; GCN-NOT: image_sample_c_d v
+; GCN-NOT: image_sample_d_cl v
+; GCN-NOT: image_sample_c_d_cl v
; GCN: branch
-; GCN: image_sample
+; GCN: image_sample_l v
+; GCN: image_sample_lz v
+; GCN: image_sample_c_lz v
+; GCN: image_sample_c_l v
+; GCN: image_sample_d v
+; GCN: image_sample_c_d v
+; GCN: image_sample_d_cl v
+; GCN: image_sample_c_d_cl v
; GCN: exp null
-define amdgpu_ps float @sinking_img_sample() {
+define amdgpu_ps float @sinking_img_sample(i1 %cond) {
main_body:
- %i = call <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 7, float undef, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
- br i1 undef, label %endif1, label %if1
+ %i1 = call <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i2 = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i3 = call <3 x float> @llvm.amdgcn.image.sample.c.lz.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i4 = call <3 x float> @llvm.amdgcn.image.sample.c.l.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i5 = call <3 x float> @llvm.amdgcn.image.sample.d.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i6 = call <3 x float> @llvm.amdgcn.image.sample.c.d.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i7 = call <3 x float> @llvm.amdgcn.image.sample.d.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i8 = call <3 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ br i1 %cond, label %endif1, label %if1
if1: ; preds = %main_body
call void @llvm.amdgcn.kill(i1 false) #4
br label %exit
endif1: ; preds = %main_body
- %i22 = extractelement <3 x float> %i, i32 2
+ %i22 = extractelement <3 x float> %i1, i32 1
%i23 = call nsz arcp contract float @llvm.fma.f32(float %i22, float 0.000000e+00, float 0.000000e+00) #1
+ %i24 = extractelement <3 x float> %i2, i32 1
+ %i25 = call nsz arcp contract float @llvm.fma.f32(float %i23, float %i24, float 0.000000e+00) #1
+ %i26 = extractelement <3 x float> %i3, i32 1
+ %i27 = call nsz arcp contract float @llvm.fma.f32(float %i25, float %i26, float 0.000000e+00) #1
+ %i28 = extractelement <3 x float> %i4, i32 1
+ %i29 = call nsz arcp contract float @llvm.fma.f32(float %i27, float %i28, float 0.000000e+00) #1
+ %i30 = extractelement <3 x float> %i5, i32 1
+ %i31 = call nsz arcp contract float @llvm.fma.f32(float %i29, float %i30, float 0.000000e+00) #1
+ %i32 = extractelement <3 x float> %i6, i32 1
+ %i33 = call nsz arcp contract float @llvm.fma.f32(float %i31, float %i32, float 0.000000e+00) #1
+ %i34 = extractelement <3 x float> %i7, i32 1
+ %i35 = call nsz arcp contract float @llvm.fma.f32(float %i33, float %i34, float 0.000000e+00) #1
+ %i36 = extractelement <3 x float> %i8, i32 1
+ %i37 = call nsz arcp contract float @llvm.fma.f32(float %i35, float %i36, float 0.000000e+00) #1
br label %exit
exit: ; preds = %endif1, %if1
- %i24 = phi float [ undef, %if1 ], [ %i23, %endif1 ]
- ret float %i24
+ %i38 = phi float [ poison, %if1 ], [ %i37, %endif1 ]
+ ret float %i38
}
+
+
+; Test that image.sample instructions which use WQM are marked as Convergent and will be left in the first block.
+
+; GCN-LABEL: {{^}}no_sinking_img_sample:
+; GCN: image_sample v
+; GCN: image_sample_c v
+; GCN: image_sample_cl v
+; GCN: image_sample_c_cl v
+; GCN: image_sample_b v
+; GCN: image_sample_c_b v
+; GCN: image_sample_b_cl v
+; GCN: branch
+; GCN-NOT: image_sample v
+; GCN-NOT: image_sample_c v
+; GCN-NOT: image_sample_cl v
+; GCN-NOT: image_sample_c_cl v
+; GCN-NOT: image_sample_b v
+; GCN-NOT: image_sample_c_b v
+; GCN-NOT: image_sample_b_cl v
+; GCN: exp null
+
+define amdgpu_ps float @no_sinking_img_sample(i1 %cond) {
+main_body:
+ %i1 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i2 = call <3 x float> @llvm.amdgcn.image.sample.c.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i3 = call <3 x float> @llvm.amdgcn.image.sample.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i4 = call <3 x float> @llvm.amdgcn.image.sample.c.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i5 = call <3 x float> @llvm.amdgcn.image.sample.b.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i6 = call <3 x float> @llvm.amdgcn.image.sample.c.b.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ %i7 = call <3 x float> @llvm.amdgcn.image.sample.b.cl.2d.v3f32.f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
+ br i1 %cond, label %endif1, label %if1
+
+if1: ; preds = %main_body
+ call void @llvm.amdgcn.kill(i1 false) #4
+ br label %exit
+
+endif1: ; preds = %main_body
+ %i22 = extractelement <3 x float> %i1, i32 2
+ %i23 = call nsz arcp contract float @llvm.fma.f32(float %i22, float 0.000000e+00, float 0.000000e+00) #1
+ %i24 = extractelement <3 x float> %i2, i32 2
+ %i25 = call nsz arcp contract float @llvm.fma.f32(float %i23, float %i24, float 0.000000e+00) #1
+ %i26 = extractelement <3 x float> %i3, i32 2
+ %i27 = call nsz arcp contract float @llvm.fma.f32(float %i25, float %i26, float 0.000000e+00) #1
+ %i28 = extractelement <3 x float> %i4, i32 2
+ %i29 = call nsz arcp contract float @llvm.fma.f32(float %i27, float %i28, float 0.000000e+00) #1
+ %i30 = extractelement <3 x float> %i5, i32 2
+ %i31 = call nsz arcp contract float @llvm.fma.f32(float %i29, float %i30, float 0.000000e+00) #1
+ %i32 = extractelement <3 x float> %i6, i32 2
+ %i33 = call nsz arcp contract float @llvm.fma.f32(float %i31, float %i32, float 0.000000e+00) #1
+ %i34 = extractelement <3 x float> %i7, i32 2
+ %i35 = call nsz arcp contract float @llvm.fma.f32(float %i33, float %i34, float 0.000000e+00) #1
+ br label %exit
+
+exit: ; preds = %endif1, %if1
+ %i36 = phi float [ poison, %if1 ], [ %i35, %endif1 ]
+ ret float %i36
+}
+
; Function Attrs: nounwind readonly willreturn
+declare <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.cl.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.cl.2d.v3f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.b.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.b.2d.v3f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.b.cl.2d.v3f32.f32.(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v3f32.f32(i32 immarg, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
declare <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.lz.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.l.2d.v3f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.d.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.d.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.d.cl.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
+declare <3 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
declare float @llvm.fma.f32(float, float, float) #2
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