[llvm] [AMDGPU][True16][MC] true16 for v_cmp_eq_f16 (PR #122943)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 14 10:47:28 PST 2025
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/122943
>From ac3ea47bebb6be2b404af54865f2ab23db4a63f2 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 14 Jan 2025 13:20:35 -0500
Subject: [PATCH] true16 for v_cmp_eq_f16
---
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 2 +-
llvm/test/CodeGen/AMDGPU/fcmp.f16.ll | 799 ++++++++++++++++++
.../AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s | 123 +--
.../MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s | 55 +-
.../test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s | 36 +-
llvm/test/MC/AMDGPU/gfx11_asm_vopc.s | 160 ++--
llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s | 216 +++--
llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s | 48 +-
llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s | 152 +++-
.../MC/AMDGPU/gfx11_asm_vopc_t16_promote.s | 156 +++-
llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s | 40 +-
llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s | 139 +--
llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s | 71 +-
llvm/test/MC/AMDGPU/gfx12_asm_vopc.s | 152 ++--
llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s | 208 +++--
llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s | 40 +-
llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s | 152 +++-
.../MC/AMDGPU/gfx12_asm_vopc_t16_promote.s | 198 +++--
.../gfx11_dasm_vop3_dpp16_from_vopc.txt | 95 ++-
.../AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt | 41 +-
.../AMDGPU/gfx11_dasm_vop3_from_vopc.txt | 24 +-
.../Disassembler/AMDGPU/gfx11_dasm_vopc.txt | 120 ++-
.../AMDGPU/gfx11_dasm_vopc_dpp16.txt | 102 ++-
.../AMDGPU/gfx11_dasm_vopc_dpp8.txt | 30 +-
.../Disassembler/AMDGPU/gfx12_dasm_vop3c.txt | 25 +-
.../AMDGPU/gfx12_dasm_vop3c_dpp16.txt | 101 ++-
.../AMDGPU/gfx12_dasm_vop3c_dpp8.txt | 47 +-
.../Disassembler/AMDGPU/gfx12_dasm_vopc.txt | 114 ++-
.../AMDGPU/gfx12_dasm_vopc_dpp16.txt | 96 ++-
.../AMDGPU/gfx12_dasm_vopc_dpp8.txt | 25 +-
30 files changed, 2734 insertions(+), 833 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 14e34c9e00ec6f..a4871663acf4ad 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -1763,7 +1763,7 @@ multiclass VOPCX_Real_t16_gfx11_gfx12<bits<9> op, string asm_name,
defm V_CMP_F_F16_fake16 : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">;
defm V_CMP_LT_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x001, "v_cmp_lt_f16">;
-defm V_CMP_EQ_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x002, "v_cmp_eq_f16">;
+defm V_CMP_EQ_F16 : VOPC_Real_t16_and_fake16_gfx11_gfx12<0x002, "v_cmp_eq_f16">;
defm V_CMP_LE_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x003, "v_cmp_le_f16">;
defm V_CMP_GT_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x004, "v_cmp_gt_f16">;
defm V_CMP_LG_F16_fake16 : VOPC_Real_t16_gfx11_gfx12<0x005, "v_cmp_lg_f16">;
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index b58996d656ecec..23b54c6741e512 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -2,6 +2,7 @@
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX12 %s
define amdgpu_kernel void @fcmp_f16_lt(
; SI-LABEL: fcmp_f16_lt:
@@ -78,6 +79,31 @@ define amdgpu_kernel void @fcmp_f16_lt(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_lt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -166,6 +192,34 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, s2
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_lt_abs:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX12-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -255,6 +309,31 @@ define amdgpu_kernel void @fcmp_f16_eq(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_eq:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -342,6 +421,31 @@ define amdgpu_kernel void @fcmp_f16_le(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_le:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -429,6 +533,31 @@ define amdgpu_kernel void @fcmp_f16_gt(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_gt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -516,6 +645,31 @@ define amdgpu_kernel void @fcmp_f16_lg(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_lg:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -603,6 +757,31 @@ define amdgpu_kernel void @fcmp_f16_ge(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_ge:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -690,6 +869,31 @@ define amdgpu_kernel void @fcmp_f16_o(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_o:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -777,6 +981,31 @@ define amdgpu_kernel void @fcmp_f16_u(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_u:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -864,6 +1093,31 @@ define amdgpu_kernel void @fcmp_f16_nge(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_nge:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -951,6 +1205,31 @@ define amdgpu_kernel void @fcmp_f16_nlg(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_nlg:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1038,6 +1317,31 @@ define amdgpu_kernel void @fcmp_f16_ngt(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_ngt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1125,6 +1429,31 @@ define amdgpu_kernel void @fcmp_f16_nle(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_nle:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1212,6 +1541,31 @@ define amdgpu_kernel void @fcmp_f16_neq(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_neq:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1299,6 +1653,31 @@ define amdgpu_kernel void @fcmp_f16_nlt(
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_f16_nlt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1401,6 +1780,36 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_lt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1504,6 +1913,36 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_eq:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_eq_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_eq_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1606,6 +2045,36 @@ define amdgpu_kernel void @fcmp_v2f16_le(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_le:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_le_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1708,6 +2177,36 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_gt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1811,6 +2310,36 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_lg:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_lg_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_lg_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -1914,6 +2443,36 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_ge:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_ge_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_ge_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2017,6 +2576,36 @@ define amdgpu_kernel void @fcmp_v2f16_o(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_o:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2120,6 +2709,36 @@ define amdgpu_kernel void @fcmp_v2f16_u(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_u:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_u_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2222,6 +2841,36 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_nge:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2324,6 +2973,36 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_nlg:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2427,6 +3106,36 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_ngt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2529,6 +3238,36 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_nle:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2631,6 +3370,36 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_neq:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_neq_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_neq_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
@@ -2733,6 +3502,36 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0
; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fcmp_v2f16_nlt:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-NEXT: s_mov_b32 s10, -1
+; GFX12-NEXT: s_mov_b32 s11, 0x31016000
+; GFX12-NEXT: s_mov_b32 s6, s10
+; GFX12-NEXT: s_mov_b32 s7, s11
+; GFX12-NEXT: s_mov_b32 s14, s10
+; GFX12-NEXT: s_mov_b32 s15, s11
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 s12, s2
+; GFX12-NEXT: s_mov_b32 s13, s3
+; GFX12-NEXT: buffer_load_b32 v0, off, s[4:7], null
+; GFX12-NEXT: buffer_load_b32 v1, off, s[12:15], null
+; GFX12-NEXT: s_mov_b32 s8, s0
+; GFX12-NEXT: s_mov_b32 s9, s1
+; GFX12-NEXT: s_wait_loadcnt 0x1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
index 798616cef66398..ec76599d2dede6 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
@@ -218,112 +218,127 @@ v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0
v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
-v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_mirror
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_mirror
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_half_mirror
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_half_mirror
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:1
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:1
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:15
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:15
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:1
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:1
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:15
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:15
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_ror:1
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_ror:1
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s105, v1, v2 row_ror:15
-// W32: v_cmp_eq_f16_e64_dpp s105, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l row_ror:15
+// W32: v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
v_cmp_eq_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
// W32: v_cmp_eq_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
index 0aa37303d62487..033d13d4837df2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
@@ -82,44 +82,59 @@ v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x01,0x7e,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
-v_cmp_eq_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x0a,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x0a,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x93,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
v_cmp_eq_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// W32: v_cmp_eq_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
index 573e3be073b345..08b9ba5daadebf 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
@@ -353,12 +353,12 @@ v_cmp_class_f64_e64 ttmp[14:15], -|src_scc|, src_scc
v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456
// GFX11: v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456 ; encoding: [0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
-v_cmp_eq_f16_e64 s5, v1, v2
-// W32: v_cmp_eq_f16_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+v_cmp_eq_f16_e64 s5, v1.l, v2.l
+// W32: v_cmp_eq_f16_e64 s5, v1.l, v2.l ; encoding: [0x05,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
-v_cmp_eq_f16_e64 s5, v255, v255
-// W32: v_cmp_eq_f16_e64 s5, v255, v255 ; encoding: [0x05,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+v_cmp_eq_f16_e64 s5, v255.l, v255.l
+// W32: v_cmp_eq_f16_e64 s5, v255.l, v255.l ; encoding: [0x05,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
v_cmp_eq_f16_e64 s5, s1, s2
@@ -409,12 +409,12 @@ v_cmp_eq_f16_e64 ttmp15, -src_scc, |vcc_lo|
// W32: v_cmp_eq_f16_e64 ttmp15, -src_scc, |vcc_lo| ; encoding: [0x7b,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
-v_cmp_eq_f16_e64 s[10:11], v1, v2
-// W64: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+v_cmp_eq_f16_e64 s[10:11], v1.l, v2.l
+// W64: v_cmp_eq_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
-v_cmp_eq_f16_e64 s[10:11], v255, v255
-// W64: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+v_cmp_eq_f16_e64 s[10:11], v255.l, v255.l
+// W64: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.l ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
v_cmp_eq_f16_e64 s[10:11], s1, s2
@@ -468,6 +468,26 @@ v_cmp_eq_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
// GFX11: v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+v_cmp_eq_f16_e64 vcc_lo, 0.5, -m0
+// W32: v_cmp_eq_f16_e64 vcc_lo, 0.5, -m0 ; encoding: [0x6a,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, v1.h, v2.l
+// W32: v_cmp_eq_f16_e64 s5, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, v255.l, v255.h
+// W32: v_cmp_eq_f16_e64 s5, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1.h, v2.l
+// W64: v_cmp_eq_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v255.l, v255.h
+// W64: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
v_cmp_eq_f32_e64 s5, v1, v2
// W32: v_cmp_eq_f32_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
index a39c2070e32628..2bd6e10e71fb17 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
@@ -340,124 +340,164 @@ v_cmp_class_f64 vcc, 0xaf123456, v255
// W64: v_cmp_class_f64_e32 vcc, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v127, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, v127.l, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, s1, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, s1, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, s105, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, s105, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, vcc_lo, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, vcc_lo, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, vcc_hi, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, vcc_hi, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, ttmp15, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, ttmp15, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, m0, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, m0, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, exec_lo, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, exec_lo, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, exec_hi, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, exec_hi, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, null, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, null, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, -1, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, -1, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, 0.5, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, 0.5, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, src_scc, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, src_scc, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, 0xfe0b, v127
-// W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+v_cmp_eq_f16 vcc_lo, 0xfe0b, v127.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2
-// W64: v_cmp_eq_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc, v1.l, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v127, v2
-// W64: v_cmp_eq_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc, v127.l, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, s1, v2
-// W64: v_cmp_eq_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, s1, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, s105, v2
-// W64: v_cmp_eq_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, s105, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, vcc_lo, v2
-// W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, vcc_lo, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, vcc_hi, v2
-// W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, vcc_hi, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, ttmp15, v2
-// W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, ttmp15, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, m0, v2
-// W64: v_cmp_eq_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, m0, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, exec_lo, v2
-// W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, exec_lo, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, exec_hi, v2
-// W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, exec_hi, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, null, v2
-// W64: v_cmp_eq_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, null, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, -1, v2
-// W64: v_cmp_eq_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, -1, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, 0.5, v2
-// W64: v_cmp_eq_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, 0.5, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, src_scc, v2
-// W64: v_cmp_eq_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, src_scc, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, 0xfe0b, v127
-// W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+v_cmp_eq_f16 vcc, 0xfe0b, v127.l
+// W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.h, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.h, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127.h, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127.h, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0.5, v127.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v127.l ; encoding: [0xf0,0xfe,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0.5, v127.l
+// W64: v_cmp_eq_f16_e32 vcc, 0.5, v127.l ; encoding: [0xf0,0xfe,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, src_scc, v2.h
+// W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, src_scc, v2.h
+// W64: v_cmp_eq_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0xfe0b, v127.h
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0xfe0b, v127.h
+// W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
v_cmp_eq_f32 vcc_lo, v1, v2
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
index fdaa9a990cb9b6..c07ee1f3ac3bac 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
@@ -228,116 +228,220 @@ v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound
// W64: v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x35,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3]
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// W32: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+v_cmp_eq_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// W32: v_cmp_eq_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
-// W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3]
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_mirror
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_half_mirror
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shl:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shl:15
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shr:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shr:15
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_ror:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_ror:15
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// W64: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+v_cmp_eq_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// W64: v_cmp_eq_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: v_cmp_eq_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: v_cmp_eq_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: v_cmp_eq_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: v_cmp_eq_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: v_cmp_eq_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xf5,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
index 97ad419a79ca84..132442f7da022e 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
@@ -52,28 +52,52 @@ v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
// W64: v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// W32: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// W32: v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// W64: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// W64: v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: v_cmp_eq_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: v_cmp_eq_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
index c48bff454deeda..06a6fa748691cc 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_cmp_class_f16_e32 vcc, v1, v255
@@ -58,71 +58,137 @@ v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255
v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16_e32 vcc, v1, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc, v1.h, v255.h
+// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v127, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc, v1.l, v255.l
+// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v128, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc, v127.h, v255.h
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.l, v255.l
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.h, v2.h
+// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.l, v2.l
+// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, vcc_hi, v255.h
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, vcc_hi, v255.l
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, vcc_lo, v255.h
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cmp_eq_f16_e32 vcc, vcc_lo, v255.l
+// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v1.h, v255.h
// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+v_cmp_eq_f16_e32 vcc_lo, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, vcc_hi, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, vcc_lo, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v1.l, v255.l
+// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v1, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.h, v255.h
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v127, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:37: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.l, v255.l
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v128, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v128.h, v2.h
+// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128.l, v2.l
+// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255.h
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255.l
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255.h
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255.l
+// GFX11: :[[@LINE-1]]:34: error: invalid operand for instruction
v_cmp_eq_i16_e32 vcc, v1, v255
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
index dc0bf7663ac179..165f0fa901eee8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
v_cmp_class_f16 vcc, v1, v255
@@ -58,71 +58,137 @@ v_cmp_class_f16 vcc, vcc_lo, v255
v_cmp_class_f16 vcc, vcc_lo, v255
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
-v_cmp_eq_f16 vcc, v1, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
+v_cmp_eq_f16 vcc, v1.h, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x01,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, v1, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
+v_cmp_eq_f16 vcc, v1.h, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x01,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_cmp_eq_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_cmp_eq_f16 vcc, v127, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
+v_cmp_eq_f16 vcc, v1.l, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, v127, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
+v_cmp_eq_f16 vcc, v1.l, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_cmp_eq_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_cmp_eq_f16 vcc, v128, v2
-// GFX11: v_cmp_eq_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
+v_cmp_eq_f16 vcc, v127.h, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x7f,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, v128, v2
-// GFX11: v_cmp_eq_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
+v_cmp_eq_f16 vcc, v127.h, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x7f,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
-v_cmp_eq_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
-// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
-v_cmp_eq_f16 vcc, vcc_hi, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+v_cmp_eq_f16 vcc, v127.l, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, vcc_hi, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+v_cmp_eq_f16 vcc, v127.l, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
-v_cmp_eq_f16 vcc, vcc_lo, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+v_cmp_eq_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
-v_cmp_eq_f16 vcc, vcc_lo, v255
-// GFX11: v_cmp_eq_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+v_cmp_eq_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+
+v_cmp_eq_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+
+v_cmp_eq_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+
+v_cmp_eq_f16 vcc, v128.h, v2.h
+// GFX11: v_cmp_eq_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x80,0x05,0x02,0x00]
+
+v_cmp_eq_f16 vcc, v128.h, v2.h
+// GFX11: v_cmp_eq_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x80,0x05,0x02,0x00]
+
+v_cmp_eq_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+
+v_cmp_eq_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+
+v_cmp_eq_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+
+v_cmp_eq_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+
+v_cmp_eq_f16 vcc, v128.l, v2.l
+// GFX11: v_cmp_eq_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
+
+v_cmp_eq_f16 vcc, v128.l, v2.l
+// GFX11: v_cmp_eq_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
+
+v_cmp_eq_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+
+v_cmp_eq_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+
+v_cmp_eq_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+
+v_cmp_eq_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_cmp_eq_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+
+v_cmp_eq_f16 vcc, vcc_hi, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_hi, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_hi, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_hi, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_lo, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_lo, v255.h
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_lo, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+
+v_cmp_eq_f16 vcc, vcc_lo, v255.l
+// GFX11: v_cmp_eq_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
v_cmp_eq_i16 vcc, v1, v255
// GFX11: v_cmp_eq_i16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x32,0xd4,0x01,0xff,0x03,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
index 177b994d5ad06f..ffa9c34b3de1a3 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
@@ -349,12 +349,12 @@ v_cmp_class_f64_e64 ttmp[14:15], -|src_scc|, src_scc
v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456
// GFX12: v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456 ; encoding: [0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
-v_cmp_eq_f16_e64 s5, v1, v2
-// W32: v_cmp_eq_f16_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+v_cmp_eq_f16_e64 s5, v1.l, v2.l
+// W32: v_cmp_eq_f16_e64 s5, v1.l, v2.l ; encoding: [0x05,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
-v_cmp_eq_f16_e64 s5, v255, v255
-// W32: v_cmp_eq_f16_e64 s5, v255, v255 ; encoding: [0x05,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+v_cmp_eq_f16_e64 s5, v255.l, v255.l
+// W32: v_cmp_eq_f16_e64 s5, v255.l, v255.l ; encoding: [0x05,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
v_cmp_eq_f16_e64 s5, s1, s2
@@ -405,13 +405,13 @@ v_cmp_eq_f16_e64 ttmp15, -src_scc, |vcc_lo|
// W32: v_cmp_eq_f16_e64 ttmp15, -src_scc, |vcc_lo| ; encoding: [0x7b,0x02,0x02,0xd4,0xfd,0xd4,0x00,0x20]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
-v_cmp_eq_f16_e64 s[10:11], v1, v2
-// W64: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+v_cmp_eq_f16_e64 s10, v1.l, v2.l
+// W32: v_cmp_eq_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
-v_cmp_eq_f16_e64 s[10:11], v255, v255
-// W64: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+v_cmp_eq_f16_e64 s10, v255.l, v255.l
+// W32: v_cmp_eq_f16_e64 s10, v255.l, v255.l ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
v_cmp_eq_f16_e64 s[10:11], s1, s2
// W64: v_cmp_eq_f16_e64 s[10:11], s1, s2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
@@ -464,6 +464,26 @@ v_cmp_eq_f16_e64 ttmp[14:15], -src_scc, |vcc_lo|
v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp
// GFX12: v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+v_cmp_eq_f16_e64 s5, v1.h, v2.l
+// W32: v_cmp_eq_f16_e64 s5, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s5, v255.l, v255.h
+// W32: v_cmp_eq_f16_e64 s5, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1.h, v2.l
+// W64: v_cmp_eq_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v255.l, v255.h
+// W64: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 vcc_lo, 0.5, -m0
+// W32: v_cmp_eq_f16_e64 vcc_lo, 0.5, -m0 ; encoding: [0x6a,0x00,0x02,0xd4,0xf0,0xfa,0x00,0x40]
+// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
+
v_cmp_eq_f32_e64 s5, v1, v2
// W32: v_cmp_eq_f32_e64 s5, v1, v2 ; encoding: [0x05,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
// W64-ERR: :[[@LINE-2]]:18: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
index 8908f18ac29bb1..90b983732515e2 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
@@ -250,128 +250,143 @@ v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0
v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX12: v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x05,0x30]
-v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, s2 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, s2 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, 2.0 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, 2.0 quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_mirror
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_mirror
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_half_mirror
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_half_mirror
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:1
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:1
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:15
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:15
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:1
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:1
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:15
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:15
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, v2 row_ror:1
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_ror:1
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s105, v1, v2 row_ror:15
-// W32: v_cmp_eq_f16_e64_dpp s105, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l row_ror:15
+// W32: v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x69,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6b,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, s2 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, s2 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, s2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x00,0x00,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, 2.0 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, 2.0 quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, 2.0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0xe8,0x01,0x00,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX12: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
+
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7b,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
v_cmp_eq_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
// W32: v_cmp_eq_f32_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
index 80ac6aa9af00e6..7e3432f2c5adae 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
@@ -114,60 +114,75 @@ v_cmp_class_f32_e64_dpp ttmp[14:15], v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX12: v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x01,0x7e,0xd4,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
-v_cmp_eq_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, s2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s5, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s5, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s5, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x02,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp s105, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp s105, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x69,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_hi, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6b,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, s2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, s2 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x02,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0]
+// GFX12: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16_e64_dpp ttmp15, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7b,0x0a,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7a,0x0a,0x02,0xd4,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
-v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX12: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x83,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x7c,0x93,0x02,0xd4,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
v_cmp_eq_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// W32: v_cmp_eq_f32_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
index 7991231aa68ed3..422e04a2335dc3 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
@@ -340,124 +340,156 @@ v_cmp_class_f64 vcc, 0xaf123456, v255
// W64: v_cmp_class_f64_e32 vcc, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v127, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, v127.l, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, s1, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, s1, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, s105, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, s105, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, vcc_lo, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, vcc_lo, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, vcc_hi, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, vcc_hi, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, ttmp15, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, ttmp15, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, m0, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, m0, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, exec_lo, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, exec_lo, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, exec_hi, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, exec_hi, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, null, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, null, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, -1, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, -1, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, 0.5, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, 0.5, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, src_scc, v2
-// W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc_lo, src_scc, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, 0xfe0b, v127
-// W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+v_cmp_eq_f16 vcc_lo, 0xfe0b, v127.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2
-// W64: v_cmp_eq_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc, v1.l, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v127, v2
-// W64: v_cmp_eq_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+v_cmp_eq_f16 vcc, v127.l, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, s1, v2
-// W64: v_cmp_eq_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, s1, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, s105, v2
-// W64: v_cmp_eq_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, s105, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, vcc_lo, v2
-// W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, vcc_lo, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, vcc_hi, v2
-// W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, vcc_hi, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, ttmp15, v2
-// W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, ttmp15, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, m0, v2
-// W64: v_cmp_eq_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, m0, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, exec_lo, v2
-// W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, exec_lo, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, exec_hi, v2
-// W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, exec_hi, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, null, v2
-// W64: v_cmp_eq_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, null, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, -1, v2
-// W64: v_cmp_eq_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, -1, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, 0.5, v2
-// W64: v_cmp_eq_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, 0.5, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, src_scc, v2
-// W64: v_cmp_eq_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+v_cmp_eq_f16 vcc, src_scc, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, 0xfe0b, v127
-// W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+v_cmp_eq_f16 vcc, 0xfe0b, v127.l
+// W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.h, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.h, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127.h, v2.l
+// W32: v_cmp_eq_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127.h, v2.l
+// W64: v_cmp_eq_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, src_scc, v2.h
+// W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, src_scc, v2.h
+// W64: v_cmp_eq_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0xfe0b, v127.h
+// W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0xfe0b, v127.h
+// W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
v_cmp_eq_f32 vcc_lo, v1, v2
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
index 54c3df6b139af9..a6a027401ab88e 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
@@ -228,116 +228,212 @@ v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound
// W64: v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x35,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3]
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3]
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// W32: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+v_cmp_eq_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// W32: v_cmp_eq_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3]
-// W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3]
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_mirror
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_half_mirror
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shl:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shl:15
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shr:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_shr:15
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_ror:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_ror:15
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// W64: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
+v_cmp_eq_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x09,0x13]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// W64: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+v_cmp_eq_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// W64: v_cmp_eq_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xf5,0x30]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W32: v_cmp_eq_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x09,0x13]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// W64: v_cmp_eq_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x09,0x13]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W32: v_cmp_eq_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xf5,0x30]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// W64: v_cmp_eq_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xf5,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
index 74147956392054..149fa48505a10a 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
@@ -52,28 +52,44 @@ v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
// W64: v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// W32: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// W32: v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// W64: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// W64: v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W32: v_cmp_eq_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// W64: v_cmp_eq_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W32: v_cmp_eq_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// W64: v_cmp_eq_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
index 8944a76fcc8018..593bd77e966176 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s
v_cmp_class_f16_e32 vcc, v1, v255
@@ -58,71 +58,137 @@ v_cmp_class_f16_e32 vcc_lo, vcc_hi, v255
v_cmp_class_f16_e32 vcc_lo, vcc_lo, v255
// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16_e32 vcc, v1, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc, v1.h, v255.h
+// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v1, v255 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v127, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc, v1.l, v255.l
+// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v127, v255 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v128, v2
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc, v127.h, v255.h
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.l, v255.l
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.h, v2.h
+// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.l, v2.l
+// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, vcc_hi, v255.h
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, vcc_hi, v255.l
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc, vcc_lo, v255.h
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cmp_eq_f16_e32 vcc, vcc_lo, v255.l
+// GFX12: :[[@LINE-1]]:31: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v1.h, v255.h
// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, v128, v2 quad_perm:[3,2,1,0]
+v_cmp_eq_f16_e32 vcc_lo, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, vcc_hi, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc, vcc_lo, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v1.l, v255.l
+// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v1, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.h, v255.h
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v127, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:37: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.l, v255.l
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v128, v2
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:35: error: invalid operand for instruction
+v_cmp_eq_f16_e32 vcc_lo, v128.h, v2.h
+// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction
-v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16_e32 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128.l, v2.l
+// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:26: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255.h
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v255.l
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255.h
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
+
+v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v255.l
+// GFX12: :[[@LINE-1]]:34: error: invalid operand for instruction
v_cmp_eq_i16_e32 vcc, v1, v255
// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
index d37859f2802b81..c7e15237b400b5 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefix=W32 %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefix=W64 %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 %s 2>&1 > /dev/null | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
@@ -80,93 +80,181 @@ v_cmp_class_f16 vcc_lo, vcc_lo, v255
// W32: v_cmp_class_f16_e64 vcc_lo, vcc_lo, v255 ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cmp_eq_f16 vcc, v1, v255
-// W64: v_cmp_eq_f16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc, v1.h, v255.h
+// W64: v_cmp_eq_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v1, v255 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.h, v255.h quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v127, v255
-// W64: v_cmp_eq_f16_e64 vcc, v127, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc, v1.l, v255.l
+// W64: v_cmp_eq_f16_e64 vcc, v1.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v127, v255 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v128, v2
-// W64: v_cmp_eq_f16_e64 vcc, v128, v2 ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc, v127.h, v255.h
+// W64: v_cmp_eq_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x7f,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, v128, v2 quad_perm:[3,2,1,0]
-// W64: v_cmp_eq_f16_e64_dpp vcc, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc, v127.h, v255.h quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, vcc_hi, v255
-// W64: v_cmp_eq_f16_e64 vcc, vcc_hi, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc, v127.l, v255.l
+// W64: v_cmp_eq_f16_e64 vcc, v127.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc, vcc_lo, v255
-// W64: v_cmp_eq_f16_e64 vcc, vcc_lo, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v1, v255
-// W32: v_cmp_eq_f16_e64 vcc_lo, v1, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128.h, v2.h
+// W64: v_cmp_eq_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x80,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128.h, v2.h quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128.l, v2.l
+// W64: v_cmp_eq_f16_e64 vcc, v128.l, v2.l ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
+// W64: v_cmp_eq_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, vcc_hi, v255.h
+// W64: v_cmp_eq_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, vcc_hi, v255.l
+// W64: v_cmp_eq_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, vcc_lo, v255.h
+// W64: v_cmp_eq_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc, vcc_lo, v255.l
+// W64: v_cmp_eq_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v1.h, v255.h
+// W32: v_cmp_eq_f16_e64 vcc_lo, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x01,0xff,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v1, v255 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v127, v255
-// W32: v_cmp_eq_f16_e64 vcc_lo, v127, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc_lo, v1.h, v255.h quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v1.l, v255.l
+// W32: v_cmp_eq_f16_e64 vcc_lo, v1.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v127, v255 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v128, v2
-// W32: v_cmp_eq_f16_e64 vcc_lo, v128, v2 ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+v_cmp_eq_f16 vcc_lo, v127.h, v255.h
+// W32: v_cmp_eq_f16_e64 vcc_lo, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x7f,0xff,0x03,0x00]
// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, v128, v2 quad_perm:[3,2,1,0]
-// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+v_cmp_eq_f16 vcc_lo, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, vcc_hi, v255
-// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_hi, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc_lo, v127.h, v255.h quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127.h, v255.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
-v_cmp_eq_f16 vcc_lo, vcc_lo, v255
-// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_lo, v255 ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+v_cmp_eq_f16 vcc_lo, v127.l, v255.l
+// W32: v_cmp_eq_f16_e64 vcc_lo, v127.l, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x7f,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128.h, v2.h
+// W32: v_cmp_eq_f16_e64 vcc_lo, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0x80,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128.h, v2.h quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128.h, v2.h op_sel:[1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x18,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128.l, v2.l
+// W32: v_cmp_eq_f16_e64 vcc_lo, v128.l, v2.l ; encoding: [0x6a,0x00,0x02,0xd4,0x80,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0]
+// W32: v_cmp_eq_f16_e64_dpp vcc_lo, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, vcc_hi, v255.h
+// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, vcc_hi, v255.l
+// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6b,0xfe,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, vcc_lo, v255.h
+// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
+
+v_cmp_eq_f16 vcc_lo, vcc_lo, v255.l
+// W32: v_cmp_eq_f16_e64 vcc_lo, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x02,0xd4,0x6a,0xfe,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:14: error: invalid operand for instruction
v_cmp_eq_i16 vcc, v1, v255
// W64: v_cmp_eq_i16_e64 vcc, v1, v255 ; encoding: [0x6a,0x00,0x32,0xd4,0x01,0xff,0x03,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
index 4e2527cc2fa2f1..d344ba1fc9ba41 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
@@ -115,59 +115,100 @@
# GFX11: v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s104, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
-# W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
-# W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
-# W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
-# W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
-# GFX11: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+
+0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+
+0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
index f399fe7f0aef4d..176119612b5611 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
@@ -43,23 +43,46 @@
# GFX11: v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s104, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
-# GFX11: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+0x7a,0x0a,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+0x7c,0x93,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
index 350087218d3668..2cff2986541564 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
@@ -186,12 +186,16 @@
# GFX11: v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456 ; encoding: [0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00
-# W32: v_cmp_eq_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-# W64: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00
-# W32: v_cmp_eq_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
-# W64: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v255.l, v255.l ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.l ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00
# W32: v_cmp_eq_f16_e64 s10, s1, s2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
@@ -244,6 +248,18 @@
0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
# GFX11: v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+
+0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+
0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00
# W32: v_cmp_eq_f32_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
# W64: v_cmp_eq_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
index 7f2de110be37d0..5357d45c2a1025 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
@@ -173,64 +173,124 @@
# W64: v_cmp_class_f64_e32 vcc, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
0x01,0x05,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
0x7f,0x05,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
0x01,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
0x69,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
0x6a,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
0x6b,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
0x7b,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
0x7d,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
0x7e,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
0x7f,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
0x7c,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
0xc1,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
0xf0,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
0xfd,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00
-# W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
-# W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+
+0x81,0x05,0x04,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x04,0x7c]
+
+0xff,0x05,0x04,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x04,0x7c]
+
+0xf0,0xfe,0x04,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0.5, v127.l ; encoding: [0xf0,0xfe,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0.5, v127.l ; encoding: [0xf0,0xfe,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0.5, v127 ; encoding: [0xf0,0xfe,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0.5, v127 ; encoding: [0xf0,0xfe,0x04,0x7c]
+
+0xfd,0x04,0x05,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x05,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x05,0x7c]
+
+0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
0x01,0x05,0x24,0x7c
# W32: v_cmp_eq_f32_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x24,0x7c]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
index da691eebd06c47..d4073617a371b0 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
@@ -117,60 +117,106 @@
# W64: v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x3d,0x30]
0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30
-# W32: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
-# W64: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64-REAL16: v_cmp_eq_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64-FAKE16: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+
+0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01]
+# W64-REAL16: v_cmp_eq_f16 vcc, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v127, v127 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x5f,0x01,0x01]
+
+0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+
+0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
+# W64-REAL16: v_cmp_eq_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
+# W64-FAKE16: v_cmp_eq_f16 vcc, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff
# W32: v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
index 998f8ea6618ca6..72e1a127ef81d1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
@@ -21,12 +21,34 @@
# W64: v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00
-# W32: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
-# W64: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+
+0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0x04,0x7c,0x7f,0x77,0x39,0x05]
+
+0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+
+0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05
# W32: v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
index aa3d3501344241..f78ff49f423352 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
@@ -182,12 +182,16 @@
# GFX12: v_cmp_class_f64_e64 null, 0xaf123456, 0xaf123456 ; encoding: [0x7c,0x00,0x7f,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00
-# W32: v_cmp_eq_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-# W64: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v1.l, v2.l ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00
-# W32: v_cmp_eq_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
-# W64: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v255.l, v255.l ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.l ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00
# W32: v_cmp_eq_f16_e64 s10, s1, s2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x00,0x00]
@@ -240,6 +244,19 @@
0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00
# GFX12: v_cmp_eq_f16_e64 null, -|0xfe0b|, -|vcc_hi| clamp ; encoding: [0x7c,0x83,0x02,0xd4,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
+0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x02,0xd4,0x01,0x05,0x02,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+
+0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00
+# W32-REAL16: v_cmp_eq_f16_e64 s10, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64 s10, v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64 s[10:11], v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x02,0xd4,0xff,0xff,0x03,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64 s[10:11], v255, v255 ; encoding: [0x0a,0x00,0x02,0xd4,0xff,0xff,0x03,0x00]
+
+
0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00
# W32: v_cmp_eq_f32_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
# W64: v_cmp_eq_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
index 487a71d59e273d..d0cd1dbb366949 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
@@ -123,63 +123,106 @@
# GFX12: v_cmp_class_f32_e64_dpp null, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xfa,0xfe,0x03,0x20,0xff,0x6f,0x0d,0x30]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, s3 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x06,0x00,0x00,0x01,0x01,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
-# W32: v_cmp_eq_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-# W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s104, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s104, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x68,0x00,0x02,0xd4,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
-# W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
-# W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x6a,0x01,0x02,0xd4,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
-# W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
-# W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
-# GFX12: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+
+0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x0a,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x7a,0x02,0x02,0xd4,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+
+0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x12,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
index 3fc6cbf4e3cd4d..2b6c0ae11b525d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
@@ -55,27 +55,52 @@
# GFX12: v_cmp_class_f32_e64_dpp null, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x01,0x7e,0xd4,0xea,0xfe,0x03,0x20,0xff,0x00,0x00,0x00]
0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp s10, v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp s[10:11], v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s10, v1.l, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s10, v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[10:11], v1.l, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[10:11], v1, s3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x02,0xd4,0xe9,0x06,0x00,0x00,0x01,0x77,0x39,0x05]
0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp s104, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp s104, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp s[104:105], v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp s[104:105], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x68,0x00,0x02,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp vcc_lo, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp vcc, |v1.l|, -v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp vcc, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x01,0x02,0xd4,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
-# GFX12: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.l| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+
+0x7a,0x0a,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
+# W32-REAL16: v_cmp_eq_f16_e64_dpp ttmp14, -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp ttmp14, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1.h, |v2.l| op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x0a,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp ttmp[14:15], -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7a,0x02,0x02,0xd4,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+
+0x7c,0x93,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
+# W32-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e64_dpp null, -|v255.l|, -|v255.h| op_sel:[0,1] clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x93,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e64_dpp null, -|v255|, -|v255| clamp dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x7c,0x83,0x02,0xd4,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
# W32: v_cmp_eq_f32_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x12,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
index 3048b8553c7ec4..01ad72033c529e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
@@ -173,64 +173,118 @@
# W64: v_cmp_class_f64_e32 vcc, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x7c,0x56,0x34,0x12,0xaf]
0x01,0x05,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v1.l, v2.l ; encoding: [0x01,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x04,0x7c]
0x7f,0x05,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v127.l, v2.l ; encoding: [0x7f,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v127, v2 ; encoding: [0x7f,0x05,0x04,0x7c]
0x01,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, s1, v2.l ; encoding: [0x01,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, s1, v2 ; encoding: [0x01,0x04,0x04,0x7c]
0x69,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, s105, v2.l ; encoding: [0x69,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, s105, v2 ; encoding: [0x69,0x04,0x04,0x7c]
0x6a,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, vcc_lo, v2 ; encoding: [0x6a,0x04,0x04,0x7c]
0x6b,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, vcc_hi, v2 ; encoding: [0x6b,0x04,0x04,0x7c]
0x7b,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, ttmp15, v2.l ; encoding: [0x7b,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, ttmp15, v2 ; encoding: [0x7b,0x04,0x04,0x7c]
0x7d,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, m0, v2.l ; encoding: [0x7d,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, m0, v2 ; encoding: [0x7d,0x04,0x04,0x7c]
0x7e,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, exec_lo, v2.l ; encoding: [0x7e,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, exec_lo, v2 ; encoding: [0x7e,0x04,0x04,0x7c]
0x7f,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, exec_hi, v2.l ; encoding: [0x7f,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, exec_hi, v2 ; encoding: [0x7f,0x04,0x04,0x7c]
0x7c,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, null, v2.l ; encoding: [0x7c,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, null, v2 ; encoding: [0x7c,0x04,0x04,0x7c]
0xc1,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, -1, v2.l ; encoding: [0xc1,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, -1, v2 ; encoding: [0xc1,0x04,0x04,0x7c]
0xf0,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0.5, v2.l ; encoding: [0xf0,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0.5, v2 ; encoding: [0xf0,0x04,0x04,0x7c]
0xfd,0x04,0x04,0x7c
-# W32: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
-# W64: v_cmp_eq_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, src_scc, v2.l ; encoding: [0xfd,0x04,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, src_scc, v2 ; encoding: [0xfd,0x04,0x04,0x7c]
0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00
-# W32: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
-# W64: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127 ; encoding: [0xff,0xfe,0x04,0x7c,0x0b,0xfe,0x00,0x00]
+
+0x81,0x05,0x04,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v1.h, v2.l ; encoding: [0x81,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x04,0x7c]
+
+0xff,0x05,0x04,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, v127.h, v2.l ; encoding: [0xff,0x05,0x04,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x04,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x04,0x7c]
+
+0xfd,0x04,0x05,0x7c
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, src_scc, v2.h ; encoding: [0xfd,0x04,0x05,0x7c]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x05,0x7c]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, src_scc, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xfd,0x04,0x05,0x7c]
+
+0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00
+# W32-REAL16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16_e32 vcc_lo, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16_e32 vcc, 0xfe0b, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ ; encoding: [0xff,0xfe,0x05,0x7c,0x0b,0xfe,0x00,0x00]
0x01,0x05,0x24,0x7c
# W32: v_cmp_eq_f32_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0x24,0x7c]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
index 213a79fdc8ed45..e9b9d8bc9ff0aa 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
@@ -117,60 +117,100 @@
# W64: v_cmp_class_f32 vcc, -|v255|, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfd,0x7c,0xff,0x6f,0x3d,0x30]
0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1b,0x00,0xff]
0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0xe4,0x00,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x40,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x41,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x01,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x0f,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x11,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x1f,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x21,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x2f,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x50,0x01,0xff]
0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x5f,0x01,0x01]
0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
-# W64: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x04,0x7c,0x01,0x60,0x01,0x13]
0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30
-# W32: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
-# W64: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64-REAL16: v_cmp_eq_f16 vcc, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+# W64-FAKE16: v_cmp_eq_f16 vcc, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x04,0x7c,0x7f,0x6f,0xfd,0x30]
+
+0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x05,0x7c,0x81,0x60,0x01,0x13]
+
+0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
+# W64-REAL16: v_cmp_eq_f16 vcc, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
+# W64-FAKE16: v_cmp_eq_f16 vcc, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/|, -|v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0x05,0x7c,0xff,0x6f,0xfd,0x30]
0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff
# W32: v_cmp_eq_f32 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x24,0x7c,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
index 3ff28315626e95..5b0dd52d4c6309 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
@@ -21,12 +21,29 @@
# W64: v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05
-# W32: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
-# W64: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x04,0x7c,0x01,0x77,0x39,0x05]
0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00
-# W32: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
-# W64: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x04,0x7c,0x7f,0x00,0x00,0x00]
+
+0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+# W64-REAL16: v_cmp_eq_f16 vcc, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v130/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x05,0x7c,0x81,0x77,0x39,0x05]
+
+0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00
+# W32-REAL16: v_cmp_eq_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+# W64-REAL16: v_cmp_eq_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+# W32-FAKE16: v_cmp_eq_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+# W64-FAKE16: v_cmp_eq_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0x05,0x7c,0xff,0x00,0x00,0x00]
+
0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05
# W32: v_cmp_eq_f32 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x24,0x7c,0x01,0x77,0x39,0x05]
More information about the llvm-commits
mailing list