[llvm] 0d71b3e - [CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)

[via llvm-commits]

Author: Jay Foad
Date: 2025-01-14T12:59:31Z
New Revision: 0d71b3e4031e7b18a5947bdea076839e5a56d202

URL: https://github.com/llvm/llvm-project/commit/0d71b3e4031e7b18a5947bdea076839e5a56d202
DIFF: https://github.com/llvm/llvm-project/commit/0d71b3e4031e7b18a5947bdea076839e5a56d202.diff

LOG: [CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    llvm/lib/CodeGen/InitUndef.cpp
    llvm/lib/CodeGen/SplitKit.cpp
    llvm/lib/CodeGen/TargetRegisterInfo.cpp
    llvm/lib/CodeGen/VirtRegMap.cpp
    llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index f4bf74c8caa5b8..0bf72637de3989 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -426,8 +426,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
   ///
   /// If this is possible, returns true and appends the best matching set of
   /// indexes to \p Indexes. If this is not possible, returns false.
-  bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI,
-                                const TargetRegisterClass *RC,
+  bool getCoveringSubRegIndexes(const TargetRegisterClass *RC,
                                 LaneBitmask LaneMask,
                                 SmallVectorImpl<unsigned> &Indexes) const;
 

diff  --git a/llvm/lib/CodeGen/InitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
index d8b3190f31003e..5fe52035d063f7 100644
--- a/llvm/lib/CodeGen/InitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -161,7 +161,7 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
     });
 
     SmallVector<unsigned> SubRegIndexNeedInsert;
-    TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, NeedDef,
+    TRI->getCoveringSubRegIndexes(TargetRegClass, NeedDef,
                                   SubRegIndexNeedInsert);
 
     // It's not possible to create the INIT_UNDEF when there is no register

diff  --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index eb33b93c197d7c..5a724805243fd8 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -568,7 +568,7 @@ SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
   SmallVector<unsigned, 8> SubIndexes;
 
   // Abort if we cannot possibly implement the COPY with the given indexes.
-  if (!TRI.getCoveringSubRegIndexes(MRI, RC, LaneMask, SubIndexes))
+  if (!TRI.getCoveringSubRegIndexes(RC, LaneMask, SubIndexes))
     report_fatal_error("Impossible to implement partial COPY");
 
   SlotIndex Def;

diff  --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index af62623ece6ab6..3be47a769d41d2 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -556,8 +556,8 @@ TargetRegisterInfo::getRegSizeInBits(Register Reg,
 }
 
 bool TargetRegisterInfo::getCoveringSubRegIndexes(
-    const MachineRegisterInfo &MRI, const TargetRegisterClass *RC,
-    LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const {
+    const TargetRegisterClass *RC, LaneBitmask LaneMask,
+    SmallVectorImpl<unsigned> &NeededIndexes) const {
   SmallVector<unsigned, 8> PossibleIndexes;
   unsigned BestIdx = 0;
   unsigned BestCover = 0;

diff  --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index d3f87f06262239..d6c020172b96b5 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -660,9 +660,9 @@ void VirtRegRewriter::rewrite() {
 
                   // TODO: Just use one super register def if none of the lanes
                   // are needed?
-                  if (!TRI->getCoveringSubRegIndexes(
-                          *MRI, MRI->getRegClass(VirtReg), LiveOutUndefLanes,
-                          CoveringIndexes))
+                  if (!TRI->getCoveringSubRegIndexes(MRI->getRegClass(VirtReg),
+                                                     LiveOutUndefLanes,
+                                                     CoveringIndexes))
                     llvm_unreachable(
                         "cannot represent required subregister defs");
 

diff  --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
index ddfa7790cabc6b..926657b8a1e7bd 100644
--- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
@@ -366,7 +366,7 @@ bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) {
 
           SmallVector<unsigned> KilledIndexes;
           bool Success = TRI->getCoveringSubRegIndexes(
-              *MRI, MRI->getRegClass(Reg), KilledMask, KilledIndexes);
+              MRI->getRegClass(Reg), KilledMask, KilledIndexes);
           (void)Success;
           assert(Success && "Failed to find subregister mask to cover lanes");
           for (unsigned SubReg : KilledIndexes) {