[llvm] ce7c881 - [AArch64] Add mayStore to more store instructions
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 14 03:14:50 PST 2025
Author: David Green
Date: 2025-01-14T11:14:45Z
New Revision: ce7c8815a1b1220905d46a6daf377b03819fd1ce
URL: https://github.com/llvm/llvm-project/commit/ce7c8815a1b1220905d46a6daf377b03819fd1ce
DIFF: https://github.com/llvm/llvm-project/commit/ce7c8815a1b1220905d46a6daf377b03819fd1ce.diff
LOG: [AArch64] Add mayStore to more store instructions
As in #121565 we need to mark all stores as mayStore, hasSideEffects is not
enough to prevent moving loads past the instructions. And marking the
instructions as mayStore is a sensible thing to do on its own.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index f527f7e4eafbc1..1ff8b77f88e273 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -5028,6 +5028,7 @@ class BaseStoreUnprivilegedLSUI<bits<2> sz, dag oops, dag iops, string asm>
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
+ let mayStore = 1;
}
multiclass StoreUnprivilegedLSUI<bits<2> sz, RegisterClass regtype, string asm> {
@@ -12532,6 +12533,7 @@ class Store64BV<bits<3> opc, string asm_inst, list<dag> pat = []>
(ins GPR64x8:$Rt, GPR64sp:$Rn), (outs GPR64:$Rs), pat> {
bits<5> Rs;
let Inst{20-16} = Rs;
+ let mayStore = 1;
}
class MOPSMemoryCopyMoveBase<bit isMove, bits<2> opcode, bits<2> op1,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 948701f897855a..c994ffd571fd4f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2799,14 +2799,17 @@ def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$
def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
+let mayLoad = 1 in
def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
(outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
+let mayStore = 1 in {
def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
(outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
(outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
let Inst{23} = 0;
}
+} // mayStore = 1
defm STG : MemTagStore<0b00, "stg">;
defm STZG : MemTagStore<0b01, "stzg">;
@@ -10018,8 +10021,10 @@ foreach i = 0-7 in {
}
let Predicates = [HasLS64] in {
+ let mayLoad = 1 in
def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),
(outs GPR64x8:$Rt)>;
+ let mayStore = 1 in
def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64x8:$Rt, GPR64sp:$Rn),
(outs)>;
def ST64BV: Store64BV<0b011, "st64bv">;
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
index 5148522431edbf..f78a9988aa0b82 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
@@ -215,12 +215,12 @@ stzgm xzr, [x2]
# CHECK-NEXT: 2 4 0.50 * U ldgm x0, [x1]
# CHECK-NEXT: 2 4 0.50 * U ldgm x1, [sp]
# CHECK-NEXT: 2 4 0.50 * U ldgm xzr, [x2]
-# CHECK-NEXT: 1 1 0.50 U stgm x0, [x1]
-# CHECK-NEXT: 1 1 0.50 U stgm x1, [sp]
-# CHECK-NEXT: 1 1 0.50 U stgm xzr, [x2]
-# CHECK-NEXT: 1 1 0.50 U stzgm x0, [x1]
-# CHECK-NEXT: 1 1 0.50 U stzgm x1, [sp]
-# CHECK-NEXT: 1 1 0.50 U stzgm xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 * U stgm x0, [x1]
+# CHECK-NEXT: 1 1 0.50 * U stgm x1, [sp]
+# CHECK-NEXT: 1 1 0.50 * U stgm xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 * U stzgm x0, [x1]
+# CHECK-NEXT: 1 1 0.50 * U stzgm x1, [sp]
+# CHECK-NEXT: 1 1 0.50 * U stzgm xzr, [x2]
# CHECK: Resources:
# CHECK-NEXT: [0.0] - Ampere1BUnitA
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
index 05b931e1444bb5..c497eec2234270 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
@@ -215,12 +215,12 @@ stzgm xzr, [x2]
# CHECK-NEXT: 1 4 0.33 * U ldgm x0, [x1]
# CHECK-NEXT: 1 4 0.33 * U ldgm x1, [sp]
# CHECK-NEXT: 1 4 0.33 * U ldgm xzr, [x2]
-# CHECK-NEXT: 2 1 0.50 U stgm x0, [x1]
-# CHECK-NEXT: 2 1 0.50 U stgm x1, [sp]
-# CHECK-NEXT: 2 1 0.50 U stgm xzr, [x2]
-# CHECK-NEXT: 2 1 0.50 U stzgm x0, [x1]
-# CHECK-NEXT: 2 1 0.50 U stzgm x1, [sp]
-# CHECK-NEXT: 2 1 0.50 U stzgm xzr, [x2]
+# CHECK-NEXT: 2 1 0.50 * U stgm x0, [x1]
+# CHECK-NEXT: 2 1 0.50 * U stgm x1, [sp]
+# CHECK-NEXT: 2 1 0.50 * U stgm xzr, [x2]
+# CHECK-NEXT: 2 1 0.50 * U stzgm x0, [x1]
+# CHECK-NEXT: 2 1 0.50 * U stzgm x1, [sp]
+# CHECK-NEXT: 2 1 0.50 * U stzgm xzr, [x2]
# CHECK: Resources:
# CHECK-NEXT: [0.0] - N2UnitB
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s
index 020d0429bd2641..132dd8eb220d49 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s
@@ -215,12 +215,12 @@ stzgm xzr, [x2]
# CHECK-NEXT: 1 4 0.33 * U ldgm x0, [x1]
# CHECK-NEXT: 1 4 0.33 * U ldgm x1, [sp]
# CHECK-NEXT: 1 4 0.33 * U ldgm xzr, [x2]
-# CHECK-NEXT: 2 1 0.50 U stgm x0, [x1]
-# CHECK-NEXT: 2 1 0.50 U stgm x1, [sp]
-# CHECK-NEXT: 2 1 0.50 U stgm xzr, [x2]
-# CHECK-NEXT: 2 1 0.50 U stzgm x0, [x1]
-# CHECK-NEXT: 2 1 0.50 U stzgm x1, [sp]
-# CHECK-NEXT: 2 1 0.50 U stzgm xzr, [x2]
+# CHECK-NEXT: 2 1 0.50 * U stgm x0, [x1]
+# CHECK-NEXT: 2 1 0.50 * U stgm x1, [sp]
+# CHECK-NEXT: 2 1 0.50 * U stgm xzr, [x2]
+# CHECK-NEXT: 2 1 0.50 * U stzgm x0, [x1]
+# CHECK-NEXT: 2 1 0.50 * U stzgm x1, [sp]
+# CHECK-NEXT: 2 1 0.50 * U stzgm xzr, [x2]
# CHECK: Resources:
# CHECK-NEXT: [0.0] - N3UnitB
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