[llvm] 87d7aeb - [RISCV][test] Add more 64-bit tests in zbb-logic-neg-imm.ll

[Piotr Fusik via llvm-commits]

Author: Piotr Fusik
Date: 2025-01-14T08:28:58+01:00
New Revision: 87d7aebdd43102160d93d8e5859228d860ea072d

URL: https://github.com/llvm/llvm-project/commit/87d7aebdd43102160d93d8e5859228d860ea072d
DIFF: https://github.com/llvm/llvm-project/commit/87d7aebdd43102160d93d8e5859228d860ea072d.diff

LOG: [RISCV][test] Add more 64-bit tests in zbb-logic-neg-imm.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
index f1e4bd09fcb928..393302c7bb5ab9 100644
--- a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
@@ -4,9 +4,9 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64,NOZBS64
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zbs -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32,ZBS
+; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32,ZBS,ZBS32
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zbs -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64,ZBS
+; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64,ZBS,ZBS64
 
 define i32 @and0xabcdefff(i32 %x) {
 ; CHECK-LABEL: and0xabcdefff:
@@ -301,8 +301,8 @@ define i64 @andimm64(i64 %x) {
   ret i64 %and
 }
 
-define i64 @andimm64srli(i64 %x) {
-; RV32-LABEL: andimm64srli:
+define i64 @orimm64srli(i64 %x) {
+; RV32-LABEL: orimm64srli:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a2, 1040384
 ; RV32-NEXT:    orn a0, a0, a2
@@ -310,7 +310,7 @@ define i64 @andimm64srli(i64 %x) {
 ; RV32-NEXT:    or a1, a1, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: andimm64srli:
+; RV64-LABEL: orimm64srli:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a1, 983040
 ; RV64-NEXT:    srli a1, a1, 3
@@ -319,3 +319,72 @@ define i64 @andimm64srli(i64 %x) {
   %or = or i64 %x, -2305843009180139521
   ret i64 %or
 }
+
+define i64 @andnofff(i64 %x) {
+; RV32-LABEL: andnofff:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a2, 1044480
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: andnofff:
+; RV64:       # %bb.0:
+; RV64-NEXT:    li a1, -1
+; RV64-NEXT:    slli a1, a1, 56
+; RV64-NEXT:    addi a1, a1, 255
+; RV64-NEXT:    and a0, a0, a1
+; RV64-NEXT:    ret
+  %and = and i64 %x, -72057594037927681
+  ret i64 %and
+}
+
+define i64 @ornofff(i64 %x) {
+; NOZBS32-LABEL: ornofff:
+; NOZBS32:       # %bb.0:
+; NOZBS32-NEXT:    lui a2, 524288
+; NOZBS32-NEXT:    or a1, a1, a2
+; NOZBS32-NEXT:    ori a0, a0, 2047
+; NOZBS32-NEXT:    ret
+;
+; NOZBS64-LABEL: ornofff:
+; NOZBS64:       # %bb.0:
+; NOZBS64-NEXT:    li a1, -1
+; NOZBS64-NEXT:    slli a1, a1, 63
+; NOZBS64-NEXT:    addi a1, a1, 2047
+; NOZBS64-NEXT:    or a0, a0, a1
+; NOZBS64-NEXT:    ret
+;
+; ZBS32-LABEL: ornofff:
+; ZBS32:       # %bb.0:
+; ZBS32-NEXT:    ori a0, a0, 2047
+; ZBS32-NEXT:    bseti a1, a1, 31
+; ZBS32-NEXT:    ret
+;
+; ZBS64-LABEL: ornofff:
+; ZBS64:       # %bb.0:
+; ZBS64-NEXT:    ori a0, a0, 2047
+; ZBS64-NEXT:    bseti a0, a0, 63
+; ZBS64-NEXT:    ret
+  %or = or i64 %x, -9223372036854773761
+  ret i64 %or
+}
+
+define i64 @xornofff(i64 %x) {
+; RV32-LABEL: xornofff:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a2, 983040
+; RV32-NEXT:    xor a1, a1, a2
+; RV32-NEXT:    xori a0, a0, 255
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: xornofff:
+; RV64:       # %bb.0:
+; RV64-NEXT:    li a1, -1
+; RV64-NEXT:    slli a1, a1, 60
+; RV64-NEXT:    addi a1, a1, 255
+; RV64-NEXT:    xor a0, a0, a1
+; RV64-NEXT:    ret
+  %xor = xor i64 %x, -1152921504606846721
+  ret i64 %xor
+}