[llvm] 9b5857a - [X86] Fix parentheses for clarity in X86ISelLowering.cpp (#121954)

[via llvm-commits]

Author: soumyaGhoshh
Date: 2025-01-14T12:19:40+05:30
New Revision: 9b5857a68381652dbea2a0c9efa734b6c4cf38c9

URL: https://github.com/llvm/llvm-project/commit/9b5857a68381652dbea2a0c9efa734b6c4cf38c9
DIFF: https://github.com/llvm/llvm-project/commit/9b5857a68381652dbea2a0c9efa734b6c4cf38c9.diff

LOG: [X86] Fix parentheses for clarity in X86ISelLowering.cpp (#121954)

fixes #121908

This pull request resolves issue #121908 by adding proper parentheses in
X86ISelLowering.cpp to follow operator precedence rules. This change
ensures better code clarity and avoids ambiguity.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 434d88db04163b..00a0aba0515f01 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -42431,7 +42431,7 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
       // Canonicalize to VPERMV if both sources are the same.
       if (V1 == V2) {
         for (int &M : Mask)
-          M = (M < 0 ? M : M & Mask.size() - 1);
+          M = (M < 0 ? M : M & (Mask.size() - 1));
         SDValue NewMask = getConstVector(Mask, MaskVT, DAG, DL,
                                          /*IsMask=*/true);
         return DAG.getNode(X86ISD::VPERMV, DL, VT, NewMask, N.getOperand(0));