[llvm] [RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. (PR #122843)

[Pengcheng Wang via llvm-commits]

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@@ -773,13 +773,18 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
           // This is a register operand. Check the register class.
           // Don't check register class if this is a tied operand, it was done
           // for the operand its tied to.
-          if (DestOperand.getTiedRegister() == -1)
+          if (DestOperand.getTiedRegister() == -1) {
             CondStream.indent(6)
-                << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n"
-                << "      (" << TargetName << "MCRegisterClasses[" << TargetName
+                << "MI.getOperand(" << OpIdx << ").isReg()";
+            if (EType == EmitterType::CheckCompress)
+              CondStream
+                  << " && MI.getOperand(" << OpIdx << ").getReg().isPhysical()";
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wangpc-pp wrote:

We may just need to add some CHECKs?

https://github.com/llvm/llvm-project/pull/122843