[llvm] [RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. (PR #122843)

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``````````bash
git-clang-format --diff 1908c41259dbd43567bb8fd32ee69862411305ef 511d0c1451741c35dd9742481a7447a8845d7ed2 --extensions cpp -- llvm/utils/TableGen/CompressInstEmitter.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 9e78abd7aa..1def8b1ab2 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -774,16 +774,15 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
           // Don't check register class if this is a tied operand, it was done
           // for the operand its tied to.
           if (DestOperand.getTiedRegister() == -1) {
-            CondStream.indent(6)
-                << "MI.getOperand(" << OpIdx << ").isReg()";
+            CondStream.indent(6) << "MI.getOperand(" << OpIdx << ").isReg()";
             if (EType == EmitterType::CheckCompress)
-              CondStream
-                  << " && MI.getOperand(" << OpIdx << ").getReg().isPhysical()";
-            CondStream << " &&\n" << indent(6)
-                << TargetName << "MCRegisterClasses[" << TargetName
-                << "::" << ClassRec->getName()
-                << "RegClassID].contains(MI.getOperand(" << OpIdx
-                << ").getReg()) &&\n";
+              CondStream << " && MI.getOperand(" << OpIdx
+                         << ").getReg().isPhysical()";
+            CondStream << " &&\n"
+                       << indent(6) << TargetName << "MCRegisterClasses["
+                       << TargetName << "::" << ClassRec->getName()
+                       << "RegClassID].contains(MI.getOperand(" << OpIdx
+                       << ").getReg()) &&\n";
           }
 
           if (CompressOrUncompress)

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https://github.com/llvm/llvm-project/pull/122843