[llvm] [RISCV] Enable Zbb ANDN/ORN/XNOR for more 64-bit constants (PR #122698)
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 13 11:54:36 PST 2025
https://github.com/pfusik updated https://github.com/llvm/llvm-project/pull/122698
>From 5bd65f0e797fbe3799b7d3de18aa406584324085 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 13 Jan 2025 12:42:39 +0100
Subject: [PATCH 1/2] [RISCV][test] Add more 64-bit tests in
zbb-logic-neg-imm.ll
---
llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll | 79 ++++++++++++++++++--
1 file changed, 74 insertions(+), 5 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
index f1e4bd09fcb928..393302c7bb5ab9 100644
--- a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
@@ -4,9 +4,9 @@
; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,NOZBS64
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zbs -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,ZBS
+; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,ZBS,ZBS32
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zbs -verify-machineinstrs < %s \
-; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,ZBS
+; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,ZBS,ZBS64
define i32 @and0xabcdefff(i32 %x) {
; CHECK-LABEL: and0xabcdefff:
@@ -301,8 +301,8 @@ define i64 @andimm64(i64 %x) {
ret i64 %and
}
-define i64 @andimm64srli(i64 %x) {
-; RV32-LABEL: andimm64srli:
+define i64 @orimm64srli(i64 %x) {
+; RV32-LABEL: orimm64srli:
; RV32: # %bb.0:
; RV32-NEXT: lui a2, 1040384
; RV32-NEXT: orn a0, a0, a2
@@ -310,7 +310,7 @@ define i64 @andimm64srli(i64 %x) {
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: ret
;
-; RV64-LABEL: andimm64srli:
+; RV64-LABEL: orimm64srli:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 983040
; RV64-NEXT: srli a1, a1, 3
@@ -319,3 +319,72 @@ define i64 @andimm64srli(i64 %x) {
%or = or i64 %x, -2305843009180139521
ret i64 %or
}
+
+define i64 @andnofff(i64 %x) {
+; RV32-LABEL: andnofff:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a2, 1044480
+; RV32-NEXT: and a1, a1, a2
+; RV32-NEXT: andi a0, a0, 255
+; RV32-NEXT: ret
+;
+; RV64-LABEL: andnofff:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: slli a1, a1, 56
+; RV64-NEXT: addi a1, a1, 255
+; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: ret
+ %and = and i64 %x, -72057594037927681
+ ret i64 %and
+}
+
+define i64 @ornofff(i64 %x) {
+; NOZBS32-LABEL: ornofff:
+; NOZBS32: # %bb.0:
+; NOZBS32-NEXT: lui a2, 524288
+; NOZBS32-NEXT: or a1, a1, a2
+; NOZBS32-NEXT: ori a0, a0, 2047
+; NOZBS32-NEXT: ret
+;
+; NOZBS64-LABEL: ornofff:
+; NOZBS64: # %bb.0:
+; NOZBS64-NEXT: li a1, -1
+; NOZBS64-NEXT: slli a1, a1, 63
+; NOZBS64-NEXT: addi a1, a1, 2047
+; NOZBS64-NEXT: or a0, a0, a1
+; NOZBS64-NEXT: ret
+;
+; ZBS32-LABEL: ornofff:
+; ZBS32: # %bb.0:
+; ZBS32-NEXT: ori a0, a0, 2047
+; ZBS32-NEXT: bseti a1, a1, 31
+; ZBS32-NEXT: ret
+;
+; ZBS64-LABEL: ornofff:
+; ZBS64: # %bb.0:
+; ZBS64-NEXT: ori a0, a0, 2047
+; ZBS64-NEXT: bseti a0, a0, 63
+; ZBS64-NEXT: ret
+ %or = or i64 %x, -9223372036854773761
+ ret i64 %or
+}
+
+define i64 @xornofff(i64 %x) {
+; RV32-LABEL: xornofff:
+; RV32: # %bb.0:
+; RV32-NEXT: lui a2, 983040
+; RV32-NEXT: xor a1, a1, a2
+; RV32-NEXT: xori a0, a0, 255
+; RV32-NEXT: ret
+;
+; RV64-LABEL: xornofff:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: slli a1, a1, 60
+; RV64-NEXT: addi a1, a1, 255
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: ret
+ %xor = xor i64 %x, -1152921504606846721
+ ret i64 %xor
+}
>From d20c4201007c3417c62105c5fb719cfe171e4875 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 13 Jan 2025 12:54:11 +0100
Subject: [PATCH 2/2] [RISCV] Enable Zbb ANDN/ORN/XNOR for more 64-bit
constants
This extends PR #120221 to 64-bit constants that don't match
the 12-low-bits-set pattern.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 7 ++++---
llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll | 21 +++++++++-----------
2 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 0070fd4520429f..9ccf95970e5b53 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3216,17 +3216,18 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
if (!isa<ConstantSDNode>(N))
return false;
-
int64_t Imm = cast<ConstantSDNode>(N)->getSExtValue();
- if ((Imm & 0xfff) != 0xfff || Imm == -1)
+
+ // For 32-bit signed constants, we can only substitute LUI+ADDI with LUI.
+ if (isInt<32>(Imm) && ((Imm & 0xfff) != 0xfff || Imm == -1))
return false;
+ // Abandon this transform if the constant is needed elsewhere.
for (const SDNode *U : N->users()) {
if (!ISD::isBitwiseLogicOp(U->getOpcode()))
return false;
}
- // For 32-bit signed constants we already know it's a win: LUI+ADDI vs LUI.
// For 64-bit constants, the instruction sequences get complex,
// so we select inverted only if it's cheaper.
if (!isInt<32>(Imm)) {
diff --git a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
index 393302c7bb5ab9..d953d34e2d7b9f 100644
--- a/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
+++ b/llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
@@ -330,10 +330,9 @@ define i64 @andnofff(i64 %x) {
;
; RV64-LABEL: andnofff:
; RV64: # %bb.0:
-; RV64-NEXT: li a1, -1
-; RV64-NEXT: slli a1, a1, 56
-; RV64-NEXT: addi a1, a1, 255
-; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: lui a1, 1048560
+; RV64-NEXT: srli a1, a1, 8
+; RV64-NEXT: andn a0, a0, a1
; RV64-NEXT: ret
%and = and i64 %x, -72057594037927681
ret i64 %and
@@ -349,10 +348,9 @@ define i64 @ornofff(i64 %x) {
;
; NOZBS64-LABEL: ornofff:
; NOZBS64: # %bb.0:
-; NOZBS64-NEXT: li a1, -1
-; NOZBS64-NEXT: slli a1, a1, 63
-; NOZBS64-NEXT: addi a1, a1, 2047
-; NOZBS64-NEXT: or a0, a0, a1
+; NOZBS64-NEXT: lui a1, 1048575
+; NOZBS64-NEXT: srli a1, a1, 1
+; NOZBS64-NEXT: orn a0, a0, a1
; NOZBS64-NEXT: ret
;
; ZBS32-LABEL: ornofff:
@@ -380,10 +378,9 @@ define i64 @xornofff(i64 %x) {
;
; RV64-LABEL: xornofff:
; RV64: # %bb.0:
-; RV64-NEXT: li a1, -1
-; RV64-NEXT: slli a1, a1, 60
-; RV64-NEXT: addi a1, a1, 255
-; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: lui a1, 1048575
+; RV64-NEXT: srli a1, a1, 4
+; RV64-NEXT: xnor a0, a0, a1
; RV64-NEXT: ret
%xor = xor i64 %x, -1152921504606846721
ret i64 %xor
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