[llvm] [SPIRV] Expand RWBuffer load and store from HLSL (PR #122355)

[Steven Perron via llvm-commits]

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@@ -1018,6 +1024,25 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
                                           MachineInstr &I) const {
   unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0;
   Register Ptr = I.getOperand(1 + OpOffset).getReg();
+
+  auto *PtrDef = getVRegDef(*MRI, Ptr);
+  auto *IntPtrDef = dyn_cast<GIntrinsic>(PtrDef);
+  if (IntPtrDef &&
+      IntPtrDef->getIntrinsicID() == Intrinsic::spv_resource_getpointer) {
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s-perron wrote:

Yes, we are relying on pattern matching, which can be easily broken. If optimizations are not run, then we will not be able to do this.

The HLSL codegen should not have a temp between the intrinsic and the load/store. There may be a temporary between the `handlefrombinding` call and the `getpointer`. If there is, then there is a store of an opaque type, which is not allowed in spir-v.

> Could reg2mem be an issue?

That pass only more values that are live across basic block boundaries, right? If so, I would not expect to create a temp between the `getpointer` and the load/store. They will be generated side-by-side.

It could add a temp between `handlefrombinding` and the `getpointer`. However, a simple call to `mem2reg` should fix that. Don't we already do that after the structurizer? 

https://github.com/llvm/llvm-project/pull/122355