[llvm] [SelectionDAG] Add an ISD node for vector.extract.last.active (PR #118810)

[Graham Hunter via llvm-commits]

huntergr-arm wrote:

A bit more experimentation shows that the 32b cap is no longer needed with the operation split across multiple operations.

The type promotion is still required, so I've improved the comment to explain why. Without it, we end up with a problem if the chosen type is illegal. For example, if we expand to a set of nodes including a `<i8> = vecreduce_umax <nxv8i8>`, that would warrant promotion of the input type to `<nxv8i16>`. If I use `setOperationAction` to set that up, then we hit an assert in `VectorLegalizer::Promote`, since it currently doesn't handle the case of a new integer vector VT being larger than the current VT -- it only wants to promote to a smaller number of wider elements. I don't think this PR is the best place to address that, so I've just chosen legal types while expanding instead.

https://github.com/llvm/llvm-project/pull/118810