[llvm] [RISCV] Support .option (no)autocompress (PR #122483)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 13 05:45:42 PST 2025
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/122483
>From 8d8ed46fbeec95c2840c612f64dbc65fb98b3f8f Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Fri, 10 Jan 2025 08:02:07 -0800
Subject: [PATCH 1/2] [RISCV] Support .option (no)autocompress
This is the implementation of a new assembler-only option to allow the
automatic compression of RISC-V instructions to be switched off without
changing the currently enabled architectural features.
This allows users better control over the autocompression feature of the
assembler, so they can get the exact instructions they want.
This will become more useful as the following things happen:
- `.option norvc` is deprecated/removed (which is sometimes used for
this purpose).
- Extensions are added where the destination instruction cannot be
disabled separately to the source instruction, either because the
destination is in the base architecture, or because it is in the same
extension as the source.
- Extensions wider than 32-bits are added, which make CompressPats more
complex to use intuitively, especially if the destination is a 32-bit
instruction.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 28 +++++++-
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 2 +
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 2 +
.../MCTargetDesc/RISCVTargetStreamer.cpp | 10 +++
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 4 ++
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++
llvm/test/MC/RISCV/option-autocompress.s | 70 +++++++++++++++++++
8 files changed, 122 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/RISCV/option-autocompress.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 2205c67c2d21ba..18794ed3b7fbf2 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3064,6 +3064,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionRVC();
setFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
return false;
}
@@ -3074,6 +3076,28 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionNoRVC();
clearFeatureBits(RISCV::FeatureStdExtC, "c");
clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
+ setFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
+ return false;
+ }
+
+ if (Option == "autocompress") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionAutoCompress();
+ clearFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
+ return false;
+ }
+
+ if (Option == "noautocompress") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionNoAutoCompress();
+ setFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
return false;
}
@@ -3326,7 +3350,9 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, getSTI());
+ bool Res = false;
+ if (!getSTI().hasFeature(RISCV::FeatureDisableAsmCompression))
+ Res = RISCVRVC::compress(CInst, Inst, getSTI());
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction((Res ? CInst : Inst), getSTI());
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index ea0e9fcde21cf9..218e0078999f30 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,6 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionAutoCompress() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoAutoCompress() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index 47df31af3057d7..33acf5828f9f4a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,6 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionAutoCompress() override;
+ void emitDirectiveOptionNoAutoCompress() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 99f57f47835abd..1e33633d1169bd 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,6 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetStreamer::emitDirectiveOptionAutoCompress() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoAutoCompress() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -122,6 +124,14 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n";
}
+void RISCVTargetAsmStreamer::emitDirectiveOptionAutoCompress() {
+ OS << "\t.option\tautocompress\n";
+}
+
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoAutoCompress() {
+ OS << "\t.option\tnoautocompress\n";
+}
+
void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
OS << "\t.option\trelax\n";
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index cb8bc21cb63557..33ab55ca855365 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,6 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoPIC();
virtual void emitDirectiveOptionRVC();
virtual void emitDirectiveOptionNoRVC();
+ virtual void emitDirectiveOptionAutoCompress();
+ virtual void emitDirectiveOptionNoAutoCompress();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -84,6 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionAutoCompress() override;
+ void emitDirectiveOptionNoAutoCompress() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index b1990409754b08..d5de046b96053c 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -254,7 +254,9 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
+ bool Res = false;
+ if (!SubtargetInfo.hasFeature(RISCV::FeatureDisableAsmCompression))
+ Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 01bc5387e672ec..a4bf4f92de27f5 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1326,6 +1326,10 @@ def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
+def FeatureDisableAsmCompression
+ : SubtargetFeature<"disable-asm-compression", "EnableAsmCompression", "false",
+ "Disable Automatic Assembly Compression.">;
+
foreach i = {1-31} in
def FeatureReserveX#i :
SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-autocompress.s
new file mode 100644
index 00000000000000..ac58a4320b2595
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-autocompress.s
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
+# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
+# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+
+# `.option (no)autocompress` enables and disables instruction compression in the
+# assembler, without changing the current architecture.
+#
+# The default is as if `.option autocompress` has been specified, that is, the
+# assembler compresses by default.
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option noautocompress
+.option noautocompress
+
+# CHECK-BYTES: 00052503
+# CHECK-INST: lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x03,0x25,0x05,0x00]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option autocompress
+.option autocompress
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
>From eba37b26f3bb88548ffcf428240c11c2370b2eae Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Mon, 13 Jan 2025 05:44:53 -0800
Subject: [PATCH 2/2] fixup! [RISCV] Support .option (no)autocompress
---
llvm/test/MC/RISCV/option-autocompress.s | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-autocompress.s
index ac58a4320b2595..d394f69af0b8ae 100644
--- a/llvm/test/MC/RISCV/option-autocompress.s
+++ b/llvm/test/MC/RISCV/option-autocompress.s
@@ -1,22 +1,22 @@
-# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c %s \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c %s \
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
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