[llvm] AMDGPU/GlobalISel: AMDGPURegBankSelect (PR #112863)

[Petar Avramovic via llvm-commits]

================
@@ -68,3 +72,37 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
 
   return std::pair(Reg, 0);
 }
+
+IntrinsicLaneMaskAnalyzer::IntrinsicLaneMaskAnalyzer(MachineFunction &MF)
+    : MRI(MF.getRegInfo()) {
+  initLaneMaskIntrinsics(MF);
+}
+
+bool IntrinsicLaneMaskAnalyzer::isS32S64LaneMask(Register Reg) const {
+  return S32S64LaneMask.contains(Reg);
+}
+
+void IntrinsicLaneMaskAnalyzer::initLaneMaskIntrinsics(MachineFunction &MF) {
+  for (auto &MBB : MF) {
+    for (auto &MI : MBB) {
+      GIntrinsic *GI = dyn_cast<GIntrinsic>(&MI);
+      if (GI && GI->is(Intrinsic::amdgcn_if_break)) {
+        S32S64LaneMask.insert(MI.getOperand(3).getReg());
+        findLCSSAPhi(MI.getOperand(0).getReg());
+      }
+
+      if (MI.getOpcode() == AMDGPU::SI_IF ||
+          MI.getOpcode() == AMDGPU::SI_ELSE) {
+        findLCSSAPhi(MI.getOperand(0).getReg());
+      }
+    }
+  }
+}
+
+void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register Reg) {
+  S32S64LaneMask.insert(Reg);
+  for (const MachineInstr &LCSSAPhi : MRI.use_instructions(Reg)) {
+    if (LCSSAPhi.isPHI())
+      S32S64LaneMask.insert(LCSSAPhi.getOperand(0).getReg());
+  }
+}
----------------
petar-avramovic wrote:

IntrinsicLaneMaskAnalyzer is very very trivial. It only handles LCSSA phis and if.break phis.

Control flow intrinsic should only be used by other control flow intrinsics. But since we run LCSSA they can also be used by lcssa-phis.

findLCSSAPhi is really meant to cover intrinsics used for control flow that are affected by LCSSA pass.
`%64:_(s32) = G_PHI %15(s32), %bb.3` is lane mask. Uniformity analysis says it is divergent. If it was S1 we would be fine but since it is S32 we need to special case put it to sgpr.

```
    %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %45(s1), %14(s32)
    SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.6

  bb.6:
    %64:_(s32) = G_PHI %15(s32), %bb.3
    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %64(s32)
    S_ENDPGM 0
```


https://github.com/llvm/llvm-project/pull/112863