[llvm] [AMDGPU] Fix unreachable reg bit width (PR #122107)

[via llvm-commits]

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@@ -0,0 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=early-machinelicm -run-pass=postmisched -o - %s | FileCheck %s
+---
+name:            test_xnull_256
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Shoreshen wrote:

Hi @arsenm , to successfully trigger bit width function in selectCOPY, the dst operand must:
1. pass `isVCC` function for the dst register of COPY
2. fails `isVCC` function for src register of the COPY

I think the bit width of src and dst must be the same, otherwise the copy mismatch type verification error will trigger

Thus to use SReg_128_XNULL as src reg class, the dst must also be 128 bit width

To pass the `isVCC` function for dst register, it must be:
1. Non physical register (which I cannot simply use $vcc as dst)
2. If it is assigned register class, the bit width must be 1
3. If it is register bank, the bank id must equals to AMDGPU::VCCRegBankID 

For COPY not being assigned for reg class, I think the dst of COPY must not be used for any instruction.

Because each instruction's each input should have a reg class bind with it, and ti will try to assign reg class accordingly.

But if COPY is not used by any instruction, then it will not be selected, since it most probably will not pass `!isTriviallyDead(MI, MRI)` function check.

So it seems like I ran out of my ways to produce a 128 case, would there be any other possibilities?

Thanks a lot!





https://github.com/llvm/llvm-project/pull/122107