[llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)

[Pengcheng Wang via llvm-commits]

================
@@ -345,9 +347,11 @@
 ; GCN-O1-NEXT:        Slot index numbering
 ; GCN-O1-NEXT:        Live Interval Analysis
 ; GCN-O1-NEXT:        Machine Natural Loop Construction
+; GCN-O1-NEXT:        Machine Register Class Info Analysis
 ; GCN-O1-NEXT:        Register Coalescer
 ; GCN-O1-NEXT:        Rename Disconnected Subregister Components
 ; GCN-O1-NEXT:        Rewrite Partial Register Uses
+; GCN-O1-NEXT:        Machine Register Class Info Analysis
----------------
wangpc-pp wrote:

It appears in the pipeline doesn't mean it will be run? The analysis result can be cached.

https://github.com/llvm/llvm-project/pull/120690