[llvm] [AMDGPU][SDAG] Try folding "lshr i64 + mad" to "mad_u64_u32" (PR #119218)

[Jay Foad via llvm-commits]

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@@ -13857,6 +13857,39 @@ static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
   return DAG.getNode(ISD::TRUNCATE, SL, VT, Mad);
 }
 
+// Fold
+//     y = lshr i64 x, 32
+//     res = add (mul i64 y, Const), x   where "Const" is a 64-bit constant
+//     with Const.hi == -1
+// To
+//     res = mad_u64_u32 y.lo ,Const.lo, x.lo
+static SDValue tryFoldMADwithSRL(SelectionDAG &DAG, const SDLoc &SL,
+                                 SDValue MulLHS, SDValue MulRHS,
+                                 SDValue AddRHS) {
+
+  if (MulLHS.getValueType() != MVT::i64 || MulLHS.getOpcode() != ISD::SRL)
+    return SDValue();
+
+  if (MulLHS.getOperand(1).getOpcode() != ISD::Constant ||
+      MulLHS.getOperand(0) != AddRHS)
+    return SDValue();
+
+  if (cast<ConstantSDNode>(MulLHS->getOperand(1))->getAsZExtVal() != 32)
+    return SDValue();
+
+  APInt Const = cast<ConstantSDNode>(MulRHS.getNode())->getAPIntValue();
+  if (!Const.isNegative() || !Const.isSignedIntN(33))
+    return SDValue();
+
+  SDValue ConstMul =
+      DAG.getConstant(Const.getZExtValue() & 0x00000000FFFFFFFF, SL, MVT::i32);
+  AddRHS = DAG.getNode(ISD::AND, SL, MVT::i64, AddRHS,
+                       DAG.getConstant(0x00000000FFFFFFFF, SL, MVT::i64));
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jayfoad wrote:

I was replying to @arsenm's question. There is no "signed case" of this optimization so the question is moot.

https://github.com/llvm/llvm-project/pull/119218