[llvm] [llvm] Remove `br i1 undef` from regression tests (PR #121733)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 5 21:30:20 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Lee Wei (leewei05)
<details>
<summary>Changes</summary>
This PR removes tests with `br i1 undef` under `llvm/tests/CodeGen/X86`. There will be more PRs in the future for this directory.
Replacing `undef` with a new function argument doesn't work in some of the tests, instead, I've replaced them with `poison`.
@<!-- -->nunoplopes @<!-- -->regehr
---
Patch is 83.79 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/121733.diff
44 Files Affected:
- (modified) llvm/test/CodeGen/X86/2011-06-03-x87chain.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll (+30-30)
- (modified) llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll (+31-31)
- (modified) llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll (+5-5)
- (modified) llvm/test/CodeGen/X86/StackColoring.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/asm-label.ll (+5-5)
- (modified) llvm/test/CodeGen/X86/avx-select.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/avx512-i1test.ll (+5-5)
- (modified) llvm/test/CodeGen/X86/block-placement.ll (+14-14)
- (modified) llvm/test/CodeGen/X86/clobber_frame_ptr.ll (+1-2)
- (modified) llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir (+3-3)
- (modified) llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir (+3-3)
- (modified) llvm/test/CodeGen/X86/combine-concatvectors.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/crash.ll (+24-24)
- (modified) llvm/test/CodeGen/X86/domain-reassignment-test.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll (+3-3)
- (modified) llvm/test/CodeGen/X86/hoist-spill.ll (+6-6)
- (modified) llvm/test/CodeGen/X86/implicit-null-checks.mir (+15-15)
- (modified) llvm/test/CodeGen/X86/interval-update-remat.ll (+3-3)
- (modified) llvm/test/CodeGen/X86/jump_sign.ll (+5-6)
- (modified) llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/lsr-delayed-fold.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll (+1-3)
- (modified) llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/misched-crash.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/pr10475.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/pr11998.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/pr32108.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/pr50254.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/pr57673.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll (+15-15)
- (modified) llvm/test/CodeGen/X86/shift-combine.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/shuffle-combine-crash.ll (+1-2)
- (modified) llvm/test/CodeGen/X86/stackmap.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/swifterror.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/switch.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/tail-merge-unreachable.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/unreachable-loop-sinking.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/update-terminator.mir (+3-3)
- (modified) llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/x86-shrink-wrapping.ll (+5-5)
``````````diff
diff --git a/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll b/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
index 67fd59ed4c2631..ed3dcad227bcd6 100644
--- a/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
+++ b/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll
@@ -30,9 +30,9 @@ entry:
ret float %conv
}
-define void @PR17495() {
+define void @PR17495(i1 %arg) {
entry:
- br i1 undef, label %while.end, label %while.body
+ br i1 %arg, label %while.end, label %while.body
while.body: ; preds = %while.body, %entry
%x.1.copyload = load i24, ptr undef, align 1
diff --git a/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll b/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
index 22bf4581c6b42a..49de5091f0e5f5 100644
--- a/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
+++ b/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll
@@ -165,7 +165,7 @@ failure: ; preds = %backedge
unreachable
}
-define void @test_04() {
+define void @test_04(i32 %arg) {
; CHECK-LABEL: test_04:
; CHECK: ## %bb.0: ## %bb
; CHECK-NEXT: ud2
@@ -175,7 +175,7 @@ bb:
bb1: ; preds = %bb10, %bb
%tmp = phi i64 [ 1, %bb ], [ %tmp2, %bb10 ]
%tmp2 = add nuw nsw i64 %tmp, 1
- br i1 undef, label %bb21, label %bb7
+ br i1 poison, label %bb21, label %bb7
bb7: ; preds = %bb1
%tmp8 = add nsw i64 %tmp, -1
@@ -187,7 +187,7 @@ bb10: ; preds = %bb16
br label %bb1
bb11: ; preds = %bb16, %bb7
- switch i32 undef, label %bb19 [
+ switch i32 %arg, label %bb19 [
i32 0, label %bb17
i32 1, label %bb16
i32 2, label %bb15
@@ -205,7 +205,7 @@ bb15: ; preds = %bb11
unreachable
bb16: ; preds = %bb11
- br i1 undef, label %bb10, label %bb11
+ br i1 poison, label %bb10, label %bb11
bb17: ; preds = %bb11
unreachable
diff --git a/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll b/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
index 86874b14b36128..d2f26c4ad1baf7 100644
--- a/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
+++ b/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll
@@ -5,13 +5,13 @@ define void @undef_2phi(ptr%buf) {
; CHECK-LABEL: @undef_2phi(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[L3:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[L3:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
-; CHECK-NEXT: br i1 undef, label [[L3]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L3]], label [[EXIT:%.*]]
; CHECK: l3:
; CHECK-NEXT: [[TMP2:%.*]] = phi x86_amx [ [[TMP1]], [[L2]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP2]])
@@ -20,16 +20,16 @@ define void @undef_2phi(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %l3
+ br i1 poison, label %l2, label %l3
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
- br i1 undef, label %l3, label %exit
+ br i1 poison, label %l3, label %exit
l3:
%t4 = phi <256 x i32> [ %t3, %l2], [ %t2, %l1 ]
@@ -45,10 +45,10 @@ define void @foo_undef(ptr%buf) {
; CHECK-LABEL: @foo_undef(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]])
@@ -57,12 +57,12 @@ define void @foo_undef(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %exit
+ br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
@@ -78,10 +78,10 @@ define void @foo_zero(ptr%buf) {
; CHECK-LABEL: @foo_zero(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ]
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]])
@@ -90,12 +90,12 @@ define void @foo_zero(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %exit
+ br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ]
@@ -112,12 +112,12 @@ define void @foo_vrow(ptr%buf, i16 %row) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 [[ROW:%.*]], i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[TMP1]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP3:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024
@@ -128,12 +128,12 @@ define void @foo_vrow(ptr%buf, i16 %row) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %exit
+ br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
@@ -150,13 +150,13 @@ define void @foo_vcol(ptr%buf, i16 %col) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 [[COL:%.*]])
; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[COL]] to i64
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 [[COL]], ptr [[TMP1]], i64 [[TMP3]], x86_amx [[T1]])
; CHECK-NEXT: [[TMP4:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP4]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024
@@ -168,12 +168,12 @@ define void @foo_vcol(ptr%buf, i16 %col) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 %col)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %exit
+ br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ]
@@ -189,12 +189,12 @@ define void @noshape(ptr%buf) {
; CHECK-LABEL: @noshape(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[BUF:%.*]], align 1024
@@ -203,12 +203,12 @@ define void @noshape(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %exit
+ br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
@@ -225,12 +225,12 @@ define void @noshape2(ptr%buf) {
; CHECK-LABEL: @noshape2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64
-; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]])
; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024
-; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]]
; CHECK: l2:
; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ]
; CHECK-NEXT: [[T6:%.*]] = call <256 x i32> @llvm.abs.v256i32(<256 x i32> [[T3]], i1 true)
@@ -240,12 +240,12 @@ define void @noshape2(ptr%buf) {
; CHECK-NEXT: ret void
;
entry:
- br i1 undef, label %l1, label %l2
+ br i1 poison, label %l1, label %l2
l1:
%t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32)
%t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
- br i1 undef, label %l2, label %exit
+ br i1 poison, label %l2, label %exit
l2:
%t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ]
diff --git a/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll b/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll
index b2eb5fd915b963..b70668f7a3dea4 100644
--- a/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll
+++ b/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll
@@ -18,14 +18,14 @@ wrapper_entry:
; Cases where amxcast can be combined across bb
; %5 and %6 is combined together since %goodphi's incoming is phi or amxcast
-define void @combine_amx_cast_and_phi() {
+define void @combine_amx_cast_and_phi(i1 %arg) {
; CHECK-LABEL: @combine_amx_cast_and_phi(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64
; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64
; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64
; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
-; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512
; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40)
@@ -43,7 +43,7 @@ define void @combine_amx_cast_and_phi() {
wrapper_entry:
%0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
%tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
- br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
+ br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -62,7 +62,7 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i,
; Cases where amxcast can't be combined across bb
; %5 and %6 is not combined together since %evilphi's incoming is not phi or amxcast
-define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) {
+define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp, i1 %arg) {
; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64
@@ -71,7 +71,7 @@ define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) {
; CHECK-NEXT: [[TMP3:%.*]] = alloca <616 x i8>, align 64
; CHECK-NEXT: [[TMP4:%.*]] = alloca <110 x i32>, align 64
; CHECK-NEXT: [[TMP5:%.*]] = add <110 x i32> [[TMP:%.*]], [[TMP]]
-; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP4]], align 512
; CHECK-NEXT: [[TMP7:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP4]], i64 40)
@@ -92,7 +92,7 @@ define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) {
;
wrapper_entry:
%0 = add <110 x i32> %tmp, %tmp
- br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
+ br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -111,7 +111,7 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i,
; Cases where amxcast can't be combined across bb
; %5 and %6 is not combined together since %evilphi's user aka %evilphi2 is not inside phi web.
-define void @fail_to_combine_amx_cast_and_phi2() {
+define void @fail_to_combine_amx_cast_and_phi2(i1 %arg) {
; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi2(
; CHECK-NEXT: wrapper_entry:
; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64
@@ -123,7 +123,7 @@ define void @fail_to_combine_amx_cast_and_phi2() {
; CHECK-NEXT: [[TMP6:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP5]], i64 40, x86_amx [[TMP6]])
; CHECK-NEXT: [[TMP8:%.*]] = load <110 x i32>, ptr [[TMP5]], align 512
-; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]]
; CHECK: for.body.i.lr.ph.i:
; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP4]], align 512
; CHECK-NEXT: [[TMP10:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP4]], i64 40)
@@ -134,13 +134,13 @@ define void @fail_to_combine_amx_cast_and_phi2() {
; CHECK-NEXT: [[TMP15:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP10]], x86_amx [[TMP12]], x86_amx [[TMP14]])
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP1]], i64 40, x86_amx [[TMP15]])
; CHECK-NEXT: [[TMP17:%.*]] = load <110 x i32>, ptr [[TMP1]], align 512
-; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]]
; CHECK: for.cond.cleanup.i.i:
; CHECK-NEXT: [[GOODPHI:%.*]] = phi <110 x i32> [ [[TMP8]], [[WRAPPER_ENTRY:%.*]] ], [ [[TMP17]], [[FOR_BODY_I_LR_PH_I]] ]
; CHECK-NEXT: store <110 x i32> [[GOODPHI]], ptr [[TMP0]], align 512
; CHECK-NEXT: [[TMP19:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP0]], i64 40)
; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP19]])
-; CHECK-NEXT: br i1 undef, label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]]
+; CHECK-NEXT: br i1 [[ARG]], label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]]
; CHECK: exit:
; CHECK-NEXT: [[EVILPHI2:%.*]] = phi <110 x i32> [ [[GOODPHI]], [[FOR_COND_CLEANUP_I_I]] ], [ [[TMP17]], [[FOR_BODY_I_LR_PH_I]] ]
; CHECK-NEXT: store <110 x i32> [[EVILPHI2]], ptr undef, align 512
@@ -149,7 +149,7 @@ define void @fail_to_combine_amx_cast_and_phi2() {
wrapper_entry:
%0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef)
%tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
- br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
+ br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i
for.body.i.lr.ph.i: ; preds = %wrapper_entry
%1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef)
@@ -157,27 +157,27 @@ for.body.i.lr.ph.i: ; preds = %wrapper_entry
%3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef)
%4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3)
%5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4)
- br i1 undef, label %for.cond.cleanup.i.i, label %exit
+ br i1 %arg, label %for.cond.cleanup.i.i, label %exit
for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, %wrapper_entry
%goodphi = phi <110 x i32> [ %tmp, %wrapper_entry ], [ %5, %for.body.i.lr.ph.i ]
%6 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %goodphi)
call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %6)
- br i1 undef, label %exit, label %for.body.i.lr.ph.i
+ br i1 %arg, label %exit, label %for.body.i.lr.ph.i
exit:
%evilphi2 = phi <110 x i32> [ %goodphi, %for.cond.cleanup.i.i ], [ %5, %for.body.i.lr.ph.i ]
store <110 x i32> %evilphi2, ptr undef, align 512
ret void
}
-define void @fail_to_combine_amx_cast_and_phi_due_to_const_value() {
+define void @fail_to_combine_amx_cast_and_phi_due_to_const_value(i1 %arg) {
; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi_due_to_const_value(
; CHECK-NEXT: wrapper_entry:
; CHECK-N...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/121733
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