[llvm] [RISCV] Don't commute with shift if it would break sh{1,2,3}add pattern (PR #119527)

[Luke Lau via llvm-commits]

lukel97 wrote:

> Can you pre-commit the following test?
> 
> ```
> ; bin/llc -mtriple=riscv64 test.ll -o -
> ; bin/llc -mtriple=riscv64 -mattr=+zba test.ll -o -
> define i32 @test(i32 %0, i32 %1) nounwind {
> entry:
>   %2 = add i32 %1, 1
>   %3 = add i32 %2, %0
>   %4 = shl nuw nsw i32 %3, 3
>   %5 = add nsw i32 %4, -8
>   ret i32 %5
> }
> ```
> 
> This regression may be fixed by checking if the RHS of the ADD is a constant.

Thanks for catching this, should be fixed now

https://github.com/llvm/llvm-project/pull/119527