[llvm] [TableGen][GISel] Learn to import patterns with physreg defs (PR #120343)

[Matt Arsenault via llvm-commits]

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@@ -801,6 +794,14 @@ def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2
 
 } // End GeneratePressureSet = 0
 
+def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
+  let CopyCost = -1;
+  let isAllocatable = 0;
+  let CrossCopyRegClass = SReg_32_XM0_XEXEC;
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arsenm wrote:

Yes, this should use one of the flavors of SReg_32. SReg_32 itself should be fine 

https://github.com/llvm/llvm-project/pull/120343