[llvm] [TableGen][GISel] Create untyped registers during instruction selection (PR #121270)

[Matt Arsenault via llvm-commits]

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@@ -3708,10 +3708,10 @@ const TargetRegisterClass *
 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
                                          const MachineRegisterInfo &MRI) const {
   const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
-  if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
+  if (const auto *RB = dyn_cast_or_null<const RegisterBank *>(RCOrRB))
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arsenm wrote:

These changes look like the consequences of not immediately setting the register class, and now other code has to be more tolerant of incomplete virtual registers. This is bad, the register should be created with a class 

https://github.com/llvm/llvm-project/pull/121270