[llvm] [RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (PR #121705)

[Luke Lau via llvm-commits]

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@@ -257,17 +257,31 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
   // Vector Unit-Stride Instructions
   // Vector Strided Instructions
   /// Dest EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL
+  case RISCV::VLE8_V:
   case RISCV::VSE8_V:
+  case RISCV::VLM_V:
+  case RISCV::VSM_V:
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lukel97 wrote:

Do we have any tests for vlm_v/vsm_v?

I think the vle/vlse/vlsxe parts are a bit more straightforward, we could split the masked loads and stores off to a separate PR

https://github.com/llvm/llvm-project/pull/121705