[lld] [LLD][COFF] Emit base relocation for native CHPE metadata pointer on ARM64X (PR #121500)
Jacek Caban via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 5 06:59:26 PST 2025
https://github.com/cjacek updated https://github.com/llvm/llvm-project/pull/121500
>From d364deaab66219a93a65a568c5526bb9880f61eb Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek at codeweavers.com>
Date: Fri, 3 Jan 2025 19:58:04 +0100
Subject: [PATCH 1/2] [LLD][COFF] Sort base relocations
This change ensures that base relocations are sorted in the output, aligning with MSVC linker behavior.
While input files typically provide sorted relocations, this update guarantees correct sorting even if
the input relocations are unordered.
---
lld/COFF/Writer.cpp | 2 +
lld/test/COFF/baserel-sort.yaml | 77 +++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
create mode 100644 lld/test/COFF/baserel-sort.yaml
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index a5b2b6238db1a9..138112f109fd43 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -2560,6 +2560,8 @@ void Writer::addBaserelBlocks(std::vector<Baserel> &v) {
const uint32_t mask = ~uint32_t(pageSize - 1);
uint32_t page = v[0].rva & mask;
size_t i = 0, j = 1;
+ llvm::sort(v,
+ [](const Baserel &x, const Baserel &y) { return x.rva < y.rva; });
for (size_t e = v.size(); j < e; ++j) {
uint32_t p = v[j].rva & mask;
if (p == page)
diff --git a/lld/test/COFF/baserel-sort.yaml b/lld/test/COFF/baserel-sort.yaml
new file mode 100644
index 00000000000000..d5affe11b2189b
--- /dev/null
+++ b/lld/test/COFF/baserel-sort.yaml
@@ -0,0 +1,77 @@
+# Verify that lld-link outputs sorted base relocations, even if the input file has unsorted entries.
+
+# RUN: yaml2obj %s -o %t.obj
+# RUN: lld-link -dll -entry:sym -machine:amd64 -out:%t.dll %t.obj
+# RUN: llvm-readobj --coff-basereloc %t.dll | FileCheck %s
+
+# CHECK: BaseReloc [
+# CHECK-NEXT: Entry {
+# CHECK-NEXT: Type: DIR64
+# CHECK-NEXT: Address: 0x2000
+# CHECK-NEXT: }
+# CHECK-NEXT: Entry {
+# CHECK-NEXT: Type: DIR64
+# CHECK-NEXT: Address: 0x2008
+# CHECK-NEXT: }
+# CHECK-NEXT: Entry {
+# CHECK-NEXT: Type: DIR64
+# CHECK-NEXT: Address: 0x2010
+# CHECK-NEXT: }
+
+--- !COFF
+header:
+ Machine: IMAGE_FILE_MACHINE_AMD64
+ Characteristics: [ ]
+sections:
+ - Name: .text
+ Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ]
+ Alignment: 4
+ SectionData: C3
+ SizeOfRawData: 1
+ - Name: .test
+ Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ]
+ Alignment: 1
+ SectionData: '000000000000000000000000000000000000000000000000'
+ SizeOfRawData: 24
+ Relocations:
+ - VirtualAddress: 16
+ SymbolName: sym
+ Type: IMAGE_REL_AMD64_ADDR64
+ - VirtualAddress: 0
+ SymbolName: sym
+ Type: IMAGE_REL_AMD64_ADDR64
+ - VirtualAddress: 8
+ SymbolName: sym
+ Type: IMAGE_REL_AMD64_ADDR64
+symbols:
+ - Name: .text
+ Value: 0
+ SectionNumber: 1
+ SimpleType: IMAGE_SYM_TYPE_NULL
+ ComplexType: IMAGE_SYM_DTYPE_NULL
+ StorageClass: IMAGE_SYM_CLASS_STATIC
+ SectionDefinition:
+ Length: 1
+ NumberOfRelocations: 0
+ NumberOfLinenumbers: 0
+ CheckSum: 40735498
+ Number: 1
+ - Name: .test
+ Value: 0
+ SectionNumber: 2
+ SimpleType: IMAGE_SYM_TYPE_NULL
+ ComplexType: IMAGE_SYM_DTYPE_NULL
+ StorageClass: IMAGE_SYM_CLASS_STATIC
+ SectionDefinition:
+ Length: 24
+ NumberOfRelocations: 3
+ NumberOfLinenumbers: 0
+ CheckSum: 0
+ Number: 2
+ - Name: sym
+ Value: 0
+ SectionNumber: 1
+ SimpleType: IMAGE_SYM_TYPE_NULL
+ ComplexType: IMAGE_SYM_DTYPE_NULL
+ StorageClass: IMAGE_SYM_CLASS_EXTERNAL
+...
>From 2a21234c233d6a32c5abd59e100e044131b71427 Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek at codeweavers.com>
Date: Mon, 9 Dec 2024 15:19:43 +0100
Subject: [PATCH 2/2] [LLD][COFF] Emit base relocation for native CHPE metadata
pointer on ARM64X
---
lld/COFF/Chunks.cpp | 16 ++++++++++++++++
lld/test/COFF/arm64x-loadconfig.s | 6 +++++-
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/lld/COFF/Chunks.cpp b/lld/COFF/Chunks.cpp
index ec0fdf0b67b38b..d87a4d8d1ae79b 100644
--- a/lld/COFF/Chunks.cpp
+++ b/lld/COFF/Chunks.cpp
@@ -564,6 +564,22 @@ void SectionChunk::getBaserels(std::vector<Baserel> *res) {
continue;
res->emplace_back(rva + rel.VirtualAddress, ty);
}
+
+ // Insert a 64-bit relocation for CHPEMetadataPointer in the native load
+ // config of a hybrid ARM64X image. Its value will be set in prepareLoadConfig
+ // to match the value in the EC load config, which is expected to be
+ // a relocatable pointer to the __chpe_metadata symbol.
+ COFFLinkerContext &ctx = file->symtab.ctx;
+ if (ctx.hybridSymtab && ctx.symtab.loadConfigSym &&
+ ctx.symtab.loadConfigSym->getChunk() == this &&
+ ctx.hybridSymtab->loadConfigSym &&
+ ctx.symtab.loadConfigSize >=
+ offsetof(coff_load_configuration64, CHPEMetadataPointer) +
+ sizeof(coff_load_configuration64::CHPEMetadataPointer))
+ res->emplace_back(
+ ctx.symtab.loadConfigSym->getRVA() +
+ offsetof(coff_load_configuration64, CHPEMetadataPointer),
+ IMAGE_REL_BASED_DIR64);
}
// MinGW specific.
diff --git a/lld/test/COFF/arm64x-loadconfig.s b/lld/test/COFF/arm64x-loadconfig.s
index d21f4bfe95b843..3b53d32a9b5492 100644
--- a/lld/test/COFF/arm64x-loadconfig.s
+++ b/lld/test/COFF/arm64x-loadconfig.s
@@ -118,10 +118,14 @@
// BASERELOC: BaseReloc [
// BASERELOC-NEXT: Entry {
// BASERELOC-NEXT: Type: DIR64
+// BASERELOC-NEXT: Address: 0x10C8
+// BASERELOC-NEXT: }
+// BASERELOC-NEXT: Entry {
+// BASERELOC-NEXT: Type: DIR64
// BASERELOC-NEXT: Address: 0x1208
// BASERELOC-NEXT: }
// BASERELOC-NEXT: Entry {
-// BASERELOC: Type: DIR64
+// BASERELOC-NEXT: Type: DIR64
// BASERELOC-NEXT: Address: 0x2074
// BASERELOC-NEXT: }
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