[llvm] [RISCV]Update CSRs (PR #121634)
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Sat Jan 4 19:30:44 PST 2025
https://github.com/dong-miao updated https://github.com/llvm/llvm-project/pull/121634
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendong24 at mails.ucas.ac.cn>
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 1/5] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920c..41b96e1497e706 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
def : SysReg<"hvip", 0x645>;
def : SysReg<"htinst", 0x64A>;
def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
//===----------------------------------------------------------------------===//
// Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
//===----------------------------------------------------------------------===//
// Machine Configuration
>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendong24 at mails.ucas.ac.cn>
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 2/5] Update rv32-hypervisor-csr-names.s
---
llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3add..79d87b3f2471cd 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
csrrs t1, vsiph, zero
# uimm12
csrrs t2, 0x254, zero
+
+##################################
+# Hypervisor Trap Setup
+##################################
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero
>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendong24 at mails.ucas.ac.cn>
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 3/5] Update rv32-machine-csr-names.s
---
llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e7..9e929b7eddeeda 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
# uimm12
csrrs t2, 0x310, zero
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
#########################
# Machine Configuration
#########################
>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendong24 at mails.ucas.ac.cn>
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 4/5] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e706..21f912bbc84d1c 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
def : SysReg<"hvip", 0x645>;
def : SysReg<"htinst", 0x64A>;
def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
def : SysReg<"hedelegh", 0x612>;
//===----------------------------------------------------------------------===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
def : SysReg<"medelegh", 0x312>;
//===----------------------------------------------------------------------===//
>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendong24 at mails.ucas.ac.cn>
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 5/5] Update rv32-only-csr-names.s
---
llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396bb..16044692101937 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system registe
csrrs t1, htimedeltah, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'htimedeltah' is RV32 only
+csrrs t1, hedelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'hedelegh' is RV32 only
+
csrrs t1, mstatush, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mstatush' is RV32 only
csrrs t1, menvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'menvcfgh' is RV32 only
csrrs t1, mseccfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mseccfgh' is RV32 only
+csrrs t1, medelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'medelegh' is RV32 only
+
csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg1' is RV32 only
csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg3' is RV32 only
csrrs t1, pmpcfg5, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg5' is RV32 only
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