[llvm] [RISCV] GISel custom lowering for G_ADD/G_SUB (PR #121587)

[Luke Quinn via llvm-commits]

================
@@ -1330,6 +1338,25 @@ bool RISCVLegalizerInfo::legalizeCustom(
       return true;
     return Helper.lowerConstant(MI);
   }
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_ADD: {
+    Helper.Observer.changingInstr(MI);
+    Helper.widenScalarSrc(MI, LLT::scalar(64), 1, TargetOpcode::G_ANYEXT);
+    Helper.widenScalarSrc(MI, LLT::scalar(64), 2, TargetOpcode::G_ANYEXT);
+
+    Register DstALU = MRI.createGenericVirtualRegister(sXLen);
+    Register DstSext = MRI.createGenericVirtualRegister(sXLen);
----------------
lquinn2015 wrote:

I am confused at to which API your referencing to. I didn't see a buildSextInReg that produces that pattern out and without that I don't know how to rewrite everything 

I need to match this this pattern 

```
%3 = G_ADD %0, %2  
```
into 
```
%4 = AnyExt %0
%5 = AnyExt %2
%6 = G_ADD %5, %4
%7 = G_SExtInReg %6
%3 = G_Trunc %8
```

But i don't have that %6  or %5 until after the final call so I don't know which API  to use. Should i make another buildSextInReg that i build myself in the code gen modules?? 

https://github.com/llvm/llvm-project/pull/121587