[llvm] [RISCV] GISel custom lowering for addiw (PR #121587)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Sat Jan 4 02:09:13 PST 2025


================
@@ -1330,6 +1338,25 @@ bool RISCVLegalizerInfo::legalizeCustom(
       return true;
     return Helper.lowerConstant(MI);
   }
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_ADD: {
+    Helper.Observer.changingInstr(MI);
+    Helper.widenScalarSrc(MI, LLT::scalar(64), 1, TargetOpcode::G_ANYEXT);
+    Helper.widenScalarSrc(MI, LLT::scalar(64), 2, TargetOpcode::G_ANYEXT);
+
+    Register DstALU = MRI.createGenericVirtualRegister(sXLen);
+    Register DstSext = MRI.createGenericVirtualRegister(sXLen);
----------------
arsenm wrote:

You should very rarely use createGenericVirtualRegister calls, fold this into `auto DstSext = buildSextInReg(sXLen)` etc 

https://github.com/llvm/llvm-project/pull/121587


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