[llvm] [X86] Add FeatureINVLPGB and CPUID handling for INVLPGB/TLBSYNC instructions (PR #121570)
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Fri Jan 3 05:37:42 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Introduced on znver3: https://reviews.llvm.org/D94134
Both instructions are available under the same CPUID bit (Fn8000_0008_EBX[INVLPGB]).
NOTE: I could use some advice on the X86TargetParser.def ordering wrt matching gcc
---
Full diff: https://github.com/llvm/llvm-project/pull/121570.diff
6 Files Affected:
- (modified) llvm/include/llvm/TargetParser/X86TargetParser.def (+1)
- (modified) llvm/lib/Target/X86/X86.td (+3)
- (modified) llvm/lib/Target/X86/X86InstrMisc.td (+3-3)
- (modified) llvm/lib/Target/X86/X86InstrPredicates.td (+1)
- (modified) llvm/lib/TargetParser/Host.cpp (+1)
- (modified) llvm/lib/TargetParser/X86TargetParser.cpp (+4-3)
``````````diff
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 5b719a2b0eb399..4eb4877f4c8b0d 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -197,6 +197,7 @@ X86_FEATURE_COMPAT(ENQCMD, "enqcmd", 0)
X86_FEATURE_COMPAT(F16C, "f16c", 0)
X86_FEATURE_COMPAT(FSGSBASE, "fsgsbase", 0)
X86_FEATURE (CRC32, "crc32")
+X86_FEATURE (INVLPGB, "invlpgb")
X86_FEATURE (INVPCID, "invpcid")
X86_FEATURE (RDPRU, "rdpru")
X86_FEATURE (SAHF, "sahf")
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 38761e1fd7eecc..f0e5de25bb9d6b 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -252,6 +252,8 @@ def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
"Enable MONITORX/MWAITX timer functionality">;
def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true",
"Enable Cache Line Zero">;
+def FeatureINVLPGB : SubtargetFeature<"invlpgb", "HasINVLPGB", "true",
+ "Support invlpgb/tlbsync instructions">;
def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
"Enable Cache Line Demote">;
def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
@@ -1565,6 +1567,7 @@ def ProcessorFeatures {
!listconcat(ZNFeatures, ZN2AdditionalFeatures);
list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
FeatureINVPCID,
+ FeatureINVLPGB,
FeaturePKU,
FeatureVAES,
FeatureVPCLMULQDQ];
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 9fabe2acf00194..0af60980820b51 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1603,11 +1603,11 @@ let SchedRW = [WriteSystem] in {
let Uses = [EAX, EDX] in
def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins),
"invlpgb", []>,
- TB, Requires<[Not64BitMode]>;
+ TB, Requires<[HasINVLPGB, Not64BitMode]>;
let Uses = [RAX, EDX] in
def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins),
"invlpgb", []>,
- TB, Requires<[In64BitMode]>;
+ TB, Requires<[HasINVLPGB, In64BitMode]>;
} // SchedRW
//===----------------------------------------------------------------------===//
@@ -1617,7 +1617,7 @@ let SchedRW = [WriteSystem] in {
let SchedRW = [WriteSystem] in {
def TLBSYNC : I<0x01, MRM_FF, (outs), (ins),
"tlbsync", []>,
- TB, Requires<[]>;
+ TB, Requires<[HasINVLPGB]>;
} // SchedRW
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index 5bdcf51be9dd84..7a105d5a9346d7 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -166,6 +166,7 @@ def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">;
def HasRDPID : Predicate<"Subtarget->hasRDPID()">;
def HasRDPRU : Predicate<"Subtarget->hasRDPRU()">;
def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">;
+def HasINVLPGB : Predicate<"Subtarget->hasINVLPGB()">;
def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">;
def HasCX8 : Predicate<"Subtarget->hasCX8()">;
def HasCX16 : Predicate<"Subtarget->hasCX16()">;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 45b4cafc995986..fd67285fbecb70 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1825,6 +1825,7 @@ const StringMap<bool> sys::getHostCPUFeatures() {
bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
!getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
+ Features["invlpgb"] = HasExtLeaf8 && ((EBX >> 3) & 1);
Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index e4b7ed7cf9b61f..a6ac6a305b0e28 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -236,9 +236,9 @@ constexpr FeatureBitset FeaturesZNVER1 =
constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
FeatureRDPID | FeatureRDPRU |
FeatureWBNOINVD;
-static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
- FeatureINVPCID | FeaturePKU |
- FeatureVAES | FeatureVPCLMULQDQ;
+static constexpr FeatureBitset FeaturesZNVER3 =
+ FeaturesZNVER2 | FeatureINVPCID | FeatureINVLPGB | FeaturePKU |
+ FeatureVAES | FeatureVPCLMULQDQ;
static constexpr FeatureBitset FeaturesZNVER4 =
FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
@@ -505,6 +505,7 @@ constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
constexpr FeatureBitset ImpliedFeaturesFXSR = {};
+constexpr FeatureBitset ImpliedFeaturesINVLPGB = {};
constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
constexpr FeatureBitset ImpliedFeaturesLWP = {};
constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
``````````
</details>
https://github.com/llvm/llvm-project/pull/121570
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