[llvm] [ARM] Record store with pre/post-indexed addressing as `mayStore` (PR #121565)
Antonio Frighetto via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 3 04:01:24 PST 2025
https://github.com/antoniofrighetto created https://github.com/llvm/llvm-project/pull/121565
A miscompilation issue observed during machine sinking has been addressed with improved handling.
Fixes: https://github.com/llvm/llvm-project/issues/121299.
>From 58ea6f11da540396c2a831d3a64b32c7f93afedc Mon Sep 17 00:00:00 2001
From: Antonio Frighetto <me at antoniofrighetto.com>
Date: Fri, 3 Jan 2025 10:41:04 +0100
Subject: [PATCH 1/2] [ARM] Introduce test for PR121565 (NFC)
---
.../ARM/sink-store-pre-load-dependency.mir | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
diff --git a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
new file mode 100644
index 00000000000000..e6e7a56d555d6c
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s
+
+name: sink-store-load-dep
+tracksRegLiveness: true
+stack:
+ - { id: 0, type: default, size: 8, alignment: 8 }
+body: |
+ bb.0:
+ ; FIXME: This is a miscompilation.
+ ; CHECK-LABEL: name: sink-store-load-dep
+ ; CHECK: bb.0:
+ ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32))
+ ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: bb.2:
+ ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16))
+ ; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg
+ %0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32))
+ %1:gpr = MOVi 55296, 14, $noreg, $noreg
+ %2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg
+ %3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16))
+ %4:gpr = MOVi 0, 14, $noreg, $noreg
+ early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg
+ %6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg
+ CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr
+ Bcc %bb.2, 3, $cpsr
+ B %bb.1
+
+ bb.1:
+ %8:gpr = MOVi 0, 14, $noreg, $noreg
+ $r0 = COPY %8:gpr
+ BX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %9:gpr = MOVi %3:gpr, 14, $noreg, $noreg
+ $r0 = COPY %9:gpr
+ BX_RET 14, $noreg, implicit $r0
+...
>From 9e9031d2772b5b3f024cf2a2ae91258f428b614b Mon Sep 17 00:00:00 2001
From: Antonio Frighetto <me at antoniofrighetto.com>
Date: Fri, 3 Jan 2025 11:01:23 +0100
Subject: [PATCH 2/2] [ARM] Record store with pre/post-indexed addressing as
`mayStore`
A miscompilation issue observed during machine sinking has been
addressed with improved handling.
Fixes: https://github.com/llvm/llvm-project/issues/121299.
---
llvm/lib/Target/ARM/ARMInstrInfo.td | 3 ++-
llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir | 7 +++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index c67177cd5a6fea..009b60c8400f02 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -3320,7 +3320,7 @@ def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
}
-
+let mayStore = 1, hasSideEffects = 0 in {
def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
StMiscFrm, IIC_iStore_bh_ru,
@@ -3352,6 +3352,7 @@ def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
let DecoderMethod = "DecodeAddrMode3Instruction";
}
+} // mayStore = 1, hasSideEffects = 0
let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
diff --git a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
index e6e7a56d555d6c..92c983e2bfd1da 100644
--- a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
+++ b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir
@@ -7,17 +7,16 @@ stack:
- { id: 0, type: default, size: 8, alignment: 8 }
body: |
bb.0:
- ; FIXME: This is a miscompilation.
; CHECK-LABEL: name: sink-store-load-dep
; CHECK: bb.0:
; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32))
; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16))
; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg
- ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2:
- ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16))
; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg
%0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32))
%1:gpr = MOVi 55296, 14, $noreg, $noreg
More information about the llvm-commits
mailing list