[llvm] f87a9db - [ARM] Expand fp64 bf16 converts similarly to f32
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 3 03:28:37 PST 2025
Author: David Green
Date: 2025-01-03T11:28:31Z
New Revision: f87a9db8322643ccbc324e317a75b55903129b55
URL: https://github.com/llvm/llvm-project/commit/f87a9db8322643ccbc324e317a75b55903129b55
DIFF: https://github.com/llvm/llvm-project/commit/f87a9db8322643ccbc324e317a75b55903129b55.diff
LOG: [ARM] Expand fp64 bf16 converts similarly to f32
This helps with +fp64 targets where the f64s are legal and not previously
lowered. It can treat fpextends as a shift + cvt and fptrunc can use a libcall.
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/bf16-instructions.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 5ec2d8389c18e5..2e517c21fc4a86 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -806,7 +806,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
} else {
setOperationAction(ISD::BF16_TO_FP, MVT::f32, Expand);
+ setOperationAction(ISD::BF16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_BF16, MVT::f32, Custom);
+ setOperationAction(ISD::FP_TO_BF16, MVT::f64, Custom);
}
for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
diff --git a/llvm/test/CodeGen/Thumb2/bf16-instructions.ll b/llvm/test/CodeGen/Thumb2/bf16-instructions.ll
index 5de7afca25b849..786e35517fd7c6 100644
--- a/llvm/test/CodeGen/Thumb2/bf16-instructions.ll
+++ b/llvm/test/CodeGen/Thumb2/bf16-instructions.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP
-; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabihf -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP
+; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabihf -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP,CHECK-FPNO64
+; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabihf -mattr=+fullfp16,+fp64 | FileCheck %s --check-prefixes=CHECK,CHECK-FP,CHECK-FP64
define bfloat @test_fadd(bfloat %a, bfloat %b) {
; CHECK-NOFP-LABEL: test_fadd:
@@ -259,9 +260,8 @@ define void @test_truncstore64(double %a, ptr %b) {
; CHECK-FP-NEXT: .save {r4, lr}
; CHECK-FP-NEXT: push {r4, lr}
; CHECK-FP-NEXT: mov r4, r0
-; CHECK-FP-NEXT: vmov r0, r1, d0
-; CHECK-FP-NEXT: bl __aeabi_d2f
-; CHECK-FP-NEXT: lsrs r0, r0, #16
+; CHECK-FP-NEXT: bl __truncdfbf2
+; CHECK-FP-NEXT: vmov r0, s0
; CHECK-FP-NEXT: strh r0, [r4]
; CHECK-FP-NEXT: pop {r4, pc}
%r = fptrunc double %a to bfloat
@@ -312,15 +312,23 @@ define double @test_loadext64(ptr %a) {
; CHECK-NOFP-NEXT: bl __aeabi_f2d
; CHECK-NOFP-NEXT: pop {r7, pc}
;
-; CHECK-FP-LABEL: test_loadext64:
-; CHECK-FP: @ %bb.0:
-; CHECK-FP-NEXT: .save {r7, lr}
-; CHECK-FP-NEXT: push {r7, lr}
-; CHECK-FP-NEXT: ldrh r0, [r0]
-; CHECK-FP-NEXT: lsls r0, r0, #16
-; CHECK-FP-NEXT: bl __aeabi_f2d
-; CHECK-FP-NEXT: vmov d0, r0, r1
-; CHECK-FP-NEXT: pop {r7, pc}
+; CHECK-FPNO64-LABEL: test_loadext64:
+; CHECK-FPNO64: @ %bb.0:
+; CHECK-FPNO64-NEXT: .save {r7, lr}
+; CHECK-FPNO64-NEXT: push {r7, lr}
+; CHECK-FPNO64-NEXT: ldrh r0, [r0]
+; CHECK-FPNO64-NEXT: lsls r0, r0, #16
+; CHECK-FPNO64-NEXT: bl __aeabi_f2d
+; CHECK-FPNO64-NEXT: vmov d0, r0, r1
+; CHECK-FPNO64-NEXT: pop {r7, pc}
+;
+; CHECK-FP64-LABEL: test_loadext64:
+; CHECK-FP64: @ %bb.0:
+; CHECK-FP64-NEXT: ldrh r0, [r0]
+; CHECK-FP64-NEXT: lsls r0, r0, #16
+; CHECK-FP64-NEXT: vmov s0, r0
+; CHECK-FP64-NEXT: vcvt.f64.f32 d0, s0
+; CHECK-FP64-NEXT: bx lr
%r = load bfloat, ptr %a
%d = fpext bfloat %r to double
ret double %d
@@ -1374,10 +1382,7 @@ define bfloat @test_fptrunc_double(double %a) {
; CHECK-FP: @ %bb.0:
; CHECK-FP-NEXT: .save {r7, lr}
; CHECK-FP-NEXT: push {r7, lr}
-; CHECK-FP-NEXT: vmov r0, r1, d0
-; CHECK-FP-NEXT: bl __aeabi_d2f
-; CHECK-FP-NEXT: lsrs r0, r0, #16
-; CHECK-FP-NEXT: vmov.f16 s0, r0
+; CHECK-FP-NEXT: bl __truncdfbf2
; CHECK-FP-NEXT: vmov.f16 r0, s0
; CHECK-FP-NEXT: vmov s0, r0
; CHECK-FP-NEXT: pop {r7, pc}
@@ -1410,15 +1415,23 @@ define double @test_fpext_double(bfloat %a) {
; CHECK-NOFP-NEXT: bl __aeabi_f2d
; CHECK-NOFP-NEXT: pop {r7, pc}
;
-; CHECK-FP-LABEL: test_fpext_double:
-; CHECK-FP: @ %bb.0:
-; CHECK-FP-NEXT: .save {r7, lr}
-; CHECK-FP-NEXT: push {r7, lr}
-; CHECK-FP-NEXT: vmov r0, s0
-; CHECK-FP-NEXT: lsls r0, r0, #16
-; CHECK-FP-NEXT: bl __aeabi_f2d
-; CHECK-FP-NEXT: vmov d0, r0, r1
-; CHECK-FP-NEXT: pop {r7, pc}
+; CHECK-FPNO64-LABEL: test_fpext_double:
+; CHECK-FPNO64: @ %bb.0:
+; CHECK-FPNO64-NEXT: .save {r7, lr}
+; CHECK-FPNO64-NEXT: push {r7, lr}
+; CHECK-FPNO64-NEXT: vmov r0, s0
+; CHECK-FPNO64-NEXT: lsls r0, r0, #16
+; CHECK-FPNO64-NEXT: bl __aeabi_f2d
+; CHECK-FPNO64-NEXT: vmov d0, r0, r1
+; CHECK-FPNO64-NEXT: pop {r7, pc}
+;
+; CHECK-FP64-LABEL: test_fpext_double:
+; CHECK-FP64: @ %bb.0:
+; CHECK-FP64-NEXT: vmov r0, s0
+; CHECK-FP64-NEXT: lsls r0, r0, #16
+; CHECK-FP64-NEXT: vmov s0, r0
+; CHECK-FP64-NEXT: vcvt.f64.f32 d0, s0
+; CHECK-FP64-NEXT: bx lr
%r = fpext bfloat %a to double
ret double %r
}
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