[llvm] [AMDGPU] Add commute for some VOP3 inst (PR #121326)

[via llvm-commits]

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@@ -15,3 +14,14 @@ body: |
     DS_WRITE2_B32_gfx9 undef %4:vgpr_32, %2, %3, 0, 1, 0, implicit $exec
 ...
 
+---
+name: test_machine_cse_op_inline_const
+body: |
+  ; GCN-LABEL: name: test_machine_cse_op_inline_const
+  ; GCN: %0:vgpr_32 = V_ADD_NC_U16_e64 0, 64, 0, -3, 1, 0, implicit $mode, implicit $exec
+  ; GCN-NEXT: DS_WRITE2_B32_gfx9 undef %2:vgpr_32, %0, %0, 0, 1, 0, implicit $exec
+  bb.0:
+    %1:vgpr_32 = V_ADD_NC_U16_e64 0, 64, 0, -3, 1, 0, implicit $mode, implicit $exec
+    %2:vgpr_32 = V_ADD_NC_U16_e64 0, -3, 0, 64, 1, 0, implicit $mode, implicit $exec
+    DS_WRITE2_B32_gfx9 undef %4:vgpr_32, %1, %2, 0, 1, 0, implicit $exec
+...
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Shoreshen wrote:

Hi, for `V_ADD_NC_U16` no e32 instruction was created, from [ISA](https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna35_instruction_set_architecture.pdf) it is only listed in VOP3 encoding in section "15.3.4. VOP3
"

https://github.com/llvm/llvm-project/pull/121326