[llvm] [AMDGPU] Add commute for some VOP3 inst (PR #121326)

[via llvm-commits]

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@@ -2785,6 +2799,9 @@ MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
   } else if (!Src0.isReg() && Src1.isReg()) {
     if (isOperandLegal(MI, Src1Idx, &Src0))
       CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
+  } else if (isInlineConstant(Src0) && isInlineConstant(Src1)) {
+    if (isOperandLegal(MI, Src1Idx, &Src0))
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Shoreshen wrote:

Hi @arsenm , sorry for replying late, it took me long time to investigate the `isOperandLegal` function.

By testing, one of the operand is inline constant and `isOperandLegal(0MI, Src1Idx, &Src0) == true` does not imply the other operand is inline constant
while src0 is true:
![2025-01-03_16-11](https://github.com/user-attachments/assets/036de53f-09e6-4dbc-97c2-030cadd941e4)
while src1 is ture:
![2025-01-03_16-25](https://github.com/user-attachments/assets/b49e4b85-4c3f-4896-aa54-9ff1b34e3f62)

It is true for VOP that if Src1 is inline constant, then Src0 is also has to be an inline constant. But the reason for that is if `OpIdx` does not consist with `MO`, the `MO` will count twice for `LiteralLimit`
![2025-01-03_16-42](https://github.com/user-attachments/assets/d9b67e8f-1135-47f1-bf0a-a5e545f986fc)

I think this may be not consistent with [ISA](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf) on section "6.12.1 Instruction Inputs" saying:
>At most one literal constant can be used, and only when an SGPR or M0 is not used as a source


https://github.com/llvm/llvm-project/pull/121326