[llvm] [X86] Generate `vpmuludq` instead of `vpmullq` (PR #121456)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512dq | FileCheck %s
+
+define <8 x i64> @pr121456(<8 x i64> %a, <8 x i64> %b) {
+; CHECK-LABEL: pr121456:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpmuludq %zmm0, %zmm1, %zmm0
+; CHECK-NEXT:    vpsllq $32, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = and <8 x i64> %a, splat (i64 4294967295)
+  %1 = and <8 x i64> %b, splat (i64 4294967295)
+  %2 = mul nuw <8 x i64> %1, %0
+  %3 = bitcast <8 x i64> %2 to <16 x i32>
+  %4 = shufflevector <16 x i32> <i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison>, <16 x i32> %3, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
+  %5 = bitcast <16 x i32> %4 to <8 x i64>
+  ret <8 x i64> %5
+}
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RKSimon wrote:

Won't this be happening for v2i64/v4i64 as well on avx512dq targets? Please can you add test coverage for those as well.

https://github.com/llvm/llvm-project/pull/121456