[llvm] [X86] Generate `vpmuludq` instead of `vpmullq` (PR #121456)

[via llvm-commits]

abhishek-kaushik22 wrote:

> > because `SimplifyDemandedVectorElts` simplifies the arguments and we fail the combine to `PMULDQ`.
> 
> Is it possible to combine the new patten instead of disble `SimplifyDemandedVectorElts`?

I'm not sure. We start with 
```
t2: v8i64,ch = CopyFromReg t0, Register:v8i64 %0
t4: v8i64,ch = CopyFromReg t0, Register:v8i64 %1
t6: v8i64 = BUILD_VECTOR Constant:i64<4294967295>, Constant:i64<4294967295>, Constant:i64<4294967295>, Constant:i64<4294967295>, Constant:i64<4294967295>, Constant:i64<4294967295>, Constant:i64<4294967295>, Constant:i64<4294967295>
t7: v8i64 = and t2, t6
t8: v8i64 = and t4, t6
t9: v8i64 = mul nuw t8, t7
```

and this gets replaced by 
```
t2: v8i64,ch = CopyFromReg t0, Register:v8i64 %0
t4: v8i64,ch = CopyFromReg t0, Register:v8i64 %1
t9: v8i64 = mul t4, t2
```
Is this safe to replace with `PMULUDQ`? We don't have any info about the `mul` being unsigned here. 

https://github.com/llvm/llvm-project/pull/121456